split Hammer doc into multiple files
This commit is contained in:
Harrison Liew
29
docs/VLSI/Advanced-Usage.rst
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29
docs/VLSI/Advanced-Usage.rst
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.. _advanced-usage:
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Advanced Usage
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==============
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Alternative RTL Flows
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---------------------
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The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
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.. code-block:: shell
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export CUSTOM_VLOG=<your verilog files>
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export VLSI_TOP=<your top module>
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Manual Step Execution & Dependency Tracking
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-------------------------------------------
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It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
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Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``.
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Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
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.. code-block:: shell
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make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
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Simulation
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----------
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With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.
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@@ -1,3 +1,5 @@
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.. _hammer:
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Core HAMMER
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================================
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@@ -67,167 +69,3 @@ Several configuration variables are needed to configure your technology of choic
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First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology.<tech_name>.tarball_dir`` or pre-installed directory with ``technology.<tech_name>.install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``.
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Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user.
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ASAP7 Tutorial
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==============
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The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins.
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Project Structure
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-----------------
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This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
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* Makefile
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* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
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* build
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* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
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* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
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* bwrc-env.yml
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* An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment.
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* example-vlsi
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* Entry point to Hammer. Contains example placeholders for hooks.
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* example.v
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* Verilog wrapper around the accelerator and dummy hard macro.
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* example.yml
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* Hammer IR for this tutorial.
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* extra_libraries
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* Contains collateral for the dummy hard macro.
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* generated-src
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* All of the elaborated Chisel and FIRRTL.
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* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
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* Core, tool, tech repositories.
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Prerequisites
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-------------
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* Python 3.4+
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* numpy and gdspy packages
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* Genus, Innovus, and Calibre licenses
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* For ASAP7 specifically:
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* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball and do not extract it
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* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision
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Initial Setup
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-------------
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In the Chipyard root, run:
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.. code-block:: shell
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``./scripts/init-vlsi.sh asap7``
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to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
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Pull the Hammer environment into the shell:
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.. code-block:: shell
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cd vlsi
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export HAMMER_HOME=$PWD/hammer
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source $HAMMER_HOME/sourceme.sh
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Building the Design
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-------------------
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To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow:
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.. code-block:: shell
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export MACROCOMPILER_MODE='--mode synflops'
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export CONFIG=Sha3RocketConfig
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export VLSI_TOP=Sha3AccelwBB
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make buildfile
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Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead.
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For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed.
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Running the VLSI Flow
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---------------------
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example-vlsi
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^^^^^^^^^^^^
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This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods.
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example.yml
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^^^^^^^^^^^
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This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
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First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK.
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Synthesis
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^^^^^^^^^
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.. code-block:: shell
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``make syn``
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
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Place-and-Route
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^^^^^^^^^^^^^^^
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.. code-block:: shell
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``make par``
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After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
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Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
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Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
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DRC & LVS
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^^^^^^^^^
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To run DRC & LVS, and view the results in Calibre:
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.. code-block:: shell
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make drc
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./build/drc-rundir/generated-scripts/view-drc
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make lvs
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./build/lvs-rundir/generated-scripts/view-lvs
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Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
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Advanced Usage
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==============
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||||
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||||
Alternative RTL Flows
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---------------------
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||||
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``.
|
||||
|
||||
.. code-block:: shell
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export CUSTOM_VLOG=<your verilog files>
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export VLSI_TOP=<your top module>
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Manual Step Execution & Dependency Tracking
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-------------------------------------------
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It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
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Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``.
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Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings:
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.. code-block:: shell
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make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps'
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Simulation
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----------
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With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design.
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137
docs/VLSI/Tutorial.rst
Normal file
137
docs/VLSI/Tutorial.rst
Normal file
@@ -0,0 +1,137 @@
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.. _tutorial:
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ASAP7 Tutorial
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==============
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The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins.
|
||||
|
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Project Structure
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-----------------
|
||||
|
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This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders:
|
||||
|
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* Makefile
|
||||
|
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* Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands.
|
||||
|
||||
* build
|
||||
|
||||
* Hammer output directory. Can be changed with the ``OBJ_DIR`` variable.
|
||||
* Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files.
|
||||
|
||||
* bwrc-env.yml
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||||
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||||
* An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment.
|
||||
|
||||
* example-vlsi
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||||
|
||||
* Entry point to Hammer. Contains example placeholders for hooks.
|
||||
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||||
* example.v
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||||
|
||||
* Verilog wrapper around the accelerator and dummy hard macro.
|
||||
|
||||
* example.yml
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||||
|
||||
* Hammer IR for this tutorial.
|
||||
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||||
* extra_libraries
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||||
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||||
* Contains collateral for the dummy hard macro.
|
||||
|
||||
* generated-src
|
||||
|
||||
* All of the elaborated Chisel and FIRRTL.
|
||||
|
||||
* hammer, hammer-<vendor>-plugins, hammer-<tech>-plugin
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||||
|
||||
* Core, tool, tech repositories.
|
||||
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||||
Prerequisites
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||||
-------------
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||||
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* Python 3.4+
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* numpy and gdspy packages
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||||
* Genus, Innovus, and Calibre licenses
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||||
* For ASAP7 specifically:
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||||
|
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* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball and do not extract it
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||||
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision
|
||||
|
||||
Initial Setup
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||||
-------------
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||||
In the Chipyard root, run:
|
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|
||||
.. code-block:: shell
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||||
|
||||
``./scripts/init-vlsi.sh asap7``
|
||||
|
||||
to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.
|
||||
|
||||
Pull the Hammer environment into the shell:
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.. code-block:: shell
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cd vlsi
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export HAMMER_HOME=$PWD/hammer
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source $HAMMER_HOME/sourceme.sh
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Building the Design
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-------------------
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To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow:
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.. code-block:: shell
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export MACROCOMPILER_MODE='--mode synflops'
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export CONFIG=Sha3RocketConfig
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export VLSI_TOP=Sha3AccelwBB
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make buildfile
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Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead.
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||||
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For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed.
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Running the VLSI Flow
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---------------------
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|
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example-vlsi
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||||
^^^^^^^^^^^^
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||||
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods.
|
||||
|
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example.yml
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||||
^^^^^^^^^^^
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||||
This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom.
|
||||
|
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First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK.
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Synthesis
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^^^^^^^^^
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.. code-block:: shell
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``make syn``
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Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP.
|
||||
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||||
Place-and-Route
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^^^^^^^^^^^^^^^
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.. code-block:: shell
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||||
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``make par``
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After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``.
|
||||
|
||||
Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes.
|
||||
|
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Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
|
||||
|
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DRC & LVS
|
||||
^^^^^^^^^
|
||||
To run DRC & LVS, and view the results in Calibre:
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.. code-block:: shell
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|
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make drc
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./build/drc-rundir/generated-scripts/view-drc
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make lvs
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./build/lvs-rundir/generated-scripts/view-lvs
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Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme <https://github.com/ucb-bar/hammer/tree/master/src/hammer-vlsi/technology/asap7>`__.
|
||||
@@ -10,3 +10,5 @@ In particular, we aim to support the HAMMER physical design generator flow.
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|
||||
Building-A-Chip
|
||||
HAMMER
|
||||
Tutorial
|
||||
Advanced-Usage
|
||||
|
||||
Reference in New Issue
Block a user