148 lines
6.6 KiB
Markdown
148 lines
6.6 KiB
Markdown
# Changelog
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This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
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## [1.3.0] - 2020-05-31
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500
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### Added
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* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. (#480)
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* A new BuildSystem key has been added, which by default builds DigitalTop (#480)
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* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). (#480)
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* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. (#480)
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* CI now checks documentation changes (#485)
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* Support FireSim multi-clock (#468)
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* Allows make variables to be injected into build system (#499)
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* Various documentation/comment updates (#511,#517,#518,#537,#533,#542,#570,#569)
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* DSPTools documentation and example (#457, #568)
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* Support for no UART configs (#536)
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* Assemble firrtl-test.jar (#551)
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* Add SPI flash configurations (#546)
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* Add Dromajo + FireSim Dromajo simulation support (#523, #553, #560)
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* NVDLA integration (#505, #559, #580)
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* Add support for Hammer Sim (#512,#581,#580,#582)
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### Changed
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* Bump FireSim to version 1.10 (#574)
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* Bump BOOM to version 3.0 (#523, #574,#580)
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* Bump Gemmini to version 0.3 (#575, #579)
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* Bump SPEC17 workload (#504, #574)
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* Bump Hwacha for fixes (#580)
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* Bump SHA3 for Linux 5.7rc3 support (#580)
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* Bump Rocket Chip to commit 1872f5d (including stage/phase compilation) (#503,#544)
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* Bump FireMarshal to version 1.9.0 (#574)
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* Chisel 3.3 and FIRRTL 1.3 (#503,#544)
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* BuildTop now builds a ChipTop dut module in the TestHarness by default (#480)
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* The default for the TOP make variable is now ChipTop (was Top) (#480)
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* Top has been renamed to DigitalTop (#480)
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* Bump libgloss (#508, #516, #580)
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* The default version of Verilator has changed to v4.034 (#547). Since this release adds enhanced support for Verilog timescales, the build detects if Verilator v4.034 or newer is visible in the build environment and sets default timescale flags appropriately.
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* Use Scalatests for FireSim CI (#528)
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* Cleanup Ariane pre-processing (#505)
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* Modify Issue Template to be more explicit (#557)
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* FireChip uses Chipyard generator (#554)
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* Have all non-synthesizeable constructs in test harness (#572)
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### Fixed
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* Aligned esp-tools spike with Gemmini (#509)
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* Fix debug rule in Verilator (#513)
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* Clean up SBT HTTP warnings (#526,#549)
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* Artefacts dropped in FireSim (#534)
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* Working IceNet + TestChipIP Unit Tests (#525)
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* Don't initialize non-existent Midas submodule (#552)
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* Verilator now supports +permissive similar to VCS (#565)
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### Deprecated
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* N/A
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### Removed
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* N/A
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## [1.2.0] - 2020-03-14
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418
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### Added
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* Ring Topology System Bus NoC (#461)
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* Integration of the Ariane core into Chipyard (#448)
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* FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427)
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* Add option to use blackboxed SimDRAM instead of SimAXIMem (#449)
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* Log `init-submodules` script (#433)
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* Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463)
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### Changed
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* Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features
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* IOBinders and BuildTop unification between FireChip and Chipyard (#390)
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* Bump BOOM to version 2.2.4 (#463)
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* Bump Gemmini to version 0.2 (#469)
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* Update to CircleCI 2.1 config. syntax and cleanup CI file (#421)
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* FireMarshal moved from FireSim to Chipyard (#415)
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* Rename config. mixins to config fragments (#451)
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### Fixed
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* `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414)
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* Fix Hetero. BOOM + Rocket + Hwacha config (#413)
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* Fix VCS stdout (#417)
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* Add a git version check to the init scripts and make them work outside of the repo root (#459)
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* Fix generation of env.sh for zsh (#435)
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* GCD example bug (#465)
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### Deprecated
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* N/A
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### Removed
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* N/A
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## [1.1.0] - 2020-01-25
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367
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### Added
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* Gemmini generator and config (PR #356 )
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* Coremark + SPEC2017 benchmarks (PR #326, #338, #344)
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* Add Hwacha tests to CI (PR #284)
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* Add Hwacha tests to benchmark and assembly test suites (PR #284)
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* Added Hwacha + Large Boom Config (PR #315)
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* Add multi-core config with a small Rocket core attached on the side (PR #361 )
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* Add UART and Test Harness UART Adapter to all configurations (PR #348)
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* User can specify $RISCV directory in build-toolchains.sh (PR #334)
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* Checksum offload in IceNet (PR #364)
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### Changed
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* Rocketchip bumped to commit [4f0cdea](https://github.com/chipsalliance/rocket-chip/tree/4f0cdea85c8a2b849fd582ccc8497892001d06b0), for chisel version 3.2.0 which includes Async reset support
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* FireSim release 1.8.0
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* FireMarshal release 1.8.0
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* BOOM release 2.2.3 (PR #397)
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* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls.
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* Add toolchain specific `env.sh` (PR #304)
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* `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308)
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* Split the VLSI build dir on type of design (PR #331)
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* Reduce Ctags runtime and only look at scala, C, C++, and Python files (PR #346)
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* Top/Top-level-traits now behave as a configurable generator (PR #347)
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* Test suite makefrag generator includes Hwacha test suites (PR #342)
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### Fixed
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* Fix VLSI makefile requirements for SRAM generation (PR #318)
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* Only filter header files from common simulation files (PR #322)
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* Bump MacroCompiler for bugfixes (PR #332)
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* commit-on-master check has specific behavior based on source branch (PR #345)
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* Makefile filtering of blackbox resource files only omits .h files (PR #322)
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* Parallel make fixed (PR #386 #392)
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### Deprecated
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* No longer need to specify `WithXTop`, default `Top` is a generator for all `Top`s (PR #347)
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### Removed
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* N/A
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## [1.0.0] - 2019-10-19
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### Added
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* This repository used to be "project-template", a template for Chisel-based projects. Through tighter integration of multiple projects from the Berkeley Architecture Research group at UC Berkeley, this repository is re-released as Chipyard - a framework for agile hardware development of RISC-V based Systems-on-Chip.
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