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1.5 KiB
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14 lines
1.5 KiB
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Rocket Core
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`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley an currently supported by `SiFive <https://www.sifive.com/>`__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
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The Rocket core supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
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It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
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Branch prediction is configurable and provided by a branch target buffer (BTB), branch history table (BHT), and a return address stack (RAS).
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For floating-point, Rocket makes use of Berkeley’s Chisel implementations of floating-point units.
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Rocket also supports the RISC-V machine, supervisor, and user privilege levels.
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A number of parameters are exposed, including the optional support of some ISA extensions (M, A, F, D), the number of floating-point pipeline stages, and the cache and TLB sizes.
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For more information, please refer to the `GitHub repository <https://github.com/freechipsproject/rocket-chip>`__, `technical report <https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.html>`__ or to `this Chisel Community Conference video <https://youtu.be/Eko86PGEoDY>`__.
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