PR comments

docs/Generators/Hwacha.rst

@@ -3,13 +3,13 @@ Hwacha
 
 The Hwacha project is developing a new vector architecture for future computer systems that are constrained in their power and energy consumption.
 The Hwacha project is inspired by traditional vector machines from the 70s and 80s, and lessons learned from our previous vector-thread architectures such as Scale and Maven
-The Hwacha project includes the Hwacha microarchitecture generator, as well as the Hwacha non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
+The Hwacha project includes the Hwacha microarchitecture generator, as well as the ``XHwacha`` non-standard RISC-V extension. Hwacha does not implement the RISC-V standard vector extension proposal.
 
 For more information on the Hwacha project, please visit the `Hwacha website <http://hwacha.org/>`__.
 
-To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config mixin to the SoC configurations. The Hwacha vector unit uses the RoCC port of a `Rocket Chip tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). 
+To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config mixin to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). 
 
-To change to configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under ``generators/hwacha/src/main/scala/configs.scala`` to see the possible configuration parameters.
+To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under ``generators/hwacha/src/main/scala/configs.scala`` to see the possible configuration parameters.
  
 Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and asseble its vector instructions.
-To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` are a fork of ``riscv-tools`` (formelty a collection of relevant software RISC-V tools) that were enhanced with the additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, esp-tools may not be up-to-date with the latest mainline version of the tools included in it.
+To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it.

docs/Generators/Rocket.rst

@@ -1,7 +1,7 @@
 Rocket Core
 ====================================
 
-`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley an currently supported by `SiFive <https://www.sifive.com/>`__. The Rocket core is used as a component (a `tile`) within the Rocket Chip SoC generator.
+`Rocket <https://github.com/freechipsproject/rocket-chip>`__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley an currently supported by `SiFive <https://www.sifive.com/>`__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
 
 The Rocket core supports the open source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
 It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.

docs/Generators/SiFive-Generators.rst

@@ -4,16 +4,16 @@ SiFive Generators
 Chipyard includes several open-source generators developed and maintained by `SiFive <https://www.sifive.com/>`__. 
 These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
 
-L2 Cache
----------
+Last-Level Cache Generator
+-----------------------------
 
-``sifive-cache`` includes an L2 cache geneator. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration.
-To learn more about configuring this L2, please refer to the :ref:`memory-hierarchy` section.
+``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration.
+To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
 
 
 Perihperal Devices
 -------------------
-``sifive-blocks`` includes multiple peripheral device generators. These include UART, SPI, PWM, JTAG, GPIO and more.
+``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
 
 These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
 To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. 
@@ -42,4 +42,4 @@ Finally, you add the relevant config mixin to the SoC config. For example:
     :start-after: DOC include start: GPIORocketConfig
     :end-before: DOC include end: GPIORocketConfig
 
-Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixin directly, but you should be aware of their addresses within the SoC address map. 
+Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixins directly, but you should be aware of their addresses within the SoC address map. 

docs/Generators/index.rst

@@ -11,7 +11,7 @@ The following pages introduce the generators integrated with the Chipyard framew
    :maxdepth: 2
    :caption: Generators:
 
-   RocketChip
+   Rocket-Chip
    Rocket
    BOOM
    Hwacha