53 lines
3.7 KiB
ReStructuredText
53 lines
3.7 KiB
ReStructuredText
.. _build-a-chip:
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Building A Chip
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===============
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In this section, we will discuss many of the ASIC-specific transforms and methodologies within Chipyard.
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For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
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Transforming the RTL
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--------------------
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Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication.
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This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Tools/Barstools:Barstools`.
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In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier.
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This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module.
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Modifying the logical hierarchy
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Building a large or complex chip often requires using hierarchical design to place and route sections of the chip separately.
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In addition, the design as written in Chipyard may not have a hierarchy that matches the physical hierarchy that would work best in the place and route tool.
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In order to reorganize the design to have its logical hierarchy match its physical hierarchy there are several FIRRTL transformations that can be run.
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These include grouping, which pull several modules into a larger one, and flattening, which dissolves a modules boundary leaving its components in its containing module.
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These transformations can be applied repeatedly to different parts of the design to arrange it as the physical designer sees fit.
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More details on how to use these transformations to reorganize the design hierarchy are forthcoming.
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Creating a floorplan
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--------------------
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An ASIC floorplan is a specification that the place-and-route tools will follow when placing instances in the design.
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This includes the top-level chip dimensions, placement of SRAM macros, placement of custom (analog) circuits, IO cell placement, bump or wirebond pad placement, blockages, hierarchical boundaries, and pin placement.
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Much of the design effort that goes into building a chip involves developing optimal floorplans for the instance of the design that is being manufactured.
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Often this is a highly manual and iterative process which consumes much of the physical designer's time.
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This cost becomes increasingly apparent as the parameterization space grows rapidly when using tools like Chisel- cycle times are hampered by the human labor
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that is required to floorplan each instance of the design.
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The Hammer team is actively developing methods of improving the agility of floorplanning for generator-based designs, like those that use Chisel.
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The libraries we are developing will emit Hammer IR that can be passed directly to the Hammer tool without the need for human intervention.
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Stay tuned for more information.
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In the meantime, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__ for information on the Hammer IR floorplan API.
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It is possible to write this IR directly, or to generate it using simple python scripts.
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While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way.
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Running the VLSI tool flow
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--------------------------
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For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation <https://hammer-vlsi.readthedocs.io/>`__.
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For an example of how to use the VLSI in the context of Chipyard, see :ref:`VLSI/ASAP7-Tutorial:ASAP7 Tutorial`.
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