91 lines
2.5 KiB
YAML
91 lines
2.5 KiB
YAML
# Override configurations in ../example-sky130.yml
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# Specify clock signals
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# Relax the clock period for OpenROAD to meet timing
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "30ns", uncertainty: "1ns"}
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]
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 4000
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height: 2500
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margins:
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left: 10
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right: 10
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top: 10
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bottom: 10
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# Place data cache SRAM instances
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_0_0"
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type: hardmacro
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x: 50
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y: 100
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_1_0"
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type: hardmacro
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x: 50
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_2_0"
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type: hardmacro
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x: 50
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y: 1300
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_3_0"
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type: hardmacro
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x: 50
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y: 1900
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_4_0"
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type: hardmacro
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x: 1000
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y: 1900
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_5_0"
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type: hardmacro
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x: 1000
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y: 1300
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_6_0"
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type: hardmacro
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x: 1000
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.dcache.data.data_arrays_0.data_arrays_0_ext.mem_7_0"
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type: hardmacro
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x: 1000
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y: 100
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orientation: r0
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# Place instruction cache SRAM instances
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_0_0"
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type: hardmacro
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x: 3250
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y: 100
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.data_arrays_0.data_arrays_0_0_ext.mem_1_0"
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type: hardmacro
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x: 3250
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y: 700
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orientation: r0
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- path: "ChipTop/system.tile_prci_domain.tile_reset_domain.tile.frontend.icache.tag_array.tag_array_ext.mem_0_0"
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type: hardmacro
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x: 3450
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y: 1300
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orientation: r0
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