357 lines
15 KiB
Markdown
357 lines
15 KiB
Markdown
# Changelog
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This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/
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## [1.7.1] - 2022-07-06
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FireSim bump for new builddriver command and various fixes. See FireSim 1.14.1 CHANGELOG.md.
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### Changed
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* Bump FireSim to 1.14.1
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## [1.7.0] - 2022-06-18
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FireSim bump for local (on-premises) FPGA and distributed metasimulation support. Hammer now supports the OpenROAD open-source EDA tools for a fully open-source RTL-to-GDS VLSI flow.
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### Added
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* Add a FireSim config with no mem port (#1172)
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* Hammer OpenROAD plugins: Yosys (syn), OpenROAD (par), Magic (drc), Netgen (lvs) (#1183)
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### Changed
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* Bump FireSim to 1.14.0
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* Give the PRCI widgets valnames to clean up module naming (#1152)
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### Fixed
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* Add missing Apache commons dependencies (fixes #1144) (#1147)
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* Disable Boost for spike (#1168)
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* VCS enhancements (#1150)
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* Support multi-thread VCS simv option like FGP, Xprof etc.
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* Idle tsi in the target thread
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* Don't shallow clone submodules (revert #1064) (#1143)
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* Remove extra spaces in FPGA makefile (#1135)
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## [1.6.3] - 2022-04-06
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FireSim bump for various fixes. Revert shallow cloning. Various CI fixes.
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### Fixed
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* Bump to FireSim 1.13.4 (changelog: https://github.com/firesim/firesim/blob/1.13.4/CHANGELOG.md#1134---2022-04-06)
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* Revert shallow cloning.
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* Various CI fixes.
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## [1.6.2] - 2022-03-01
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Minor fixes to FireSim.
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### Fixed
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* Bump to FireSim 1.13.3 (#1134)
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## [1.6.1] - 2022-03-01
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Minor fixes to FireSim.
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### Fixed
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* Bump to FireSim 1.13.2 (#1133)
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## [1.6.0] - 2022-02-15
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/913
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### Added
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* Diplomatic IOBinder-like approach to setting up PRCI across different deployment targets (#900)
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* Default set of MMIO-controlled reset-setters and clock-gaters (#900)
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* Added simulation makefile options `torture` and `torture-overnight` for running Torture (#992)
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* FSDB waveform support (#1072, #1102)
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* Use GitHub Actions for CI (#1004, #999, #1090, #1092)
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* Add MAKE variable in `build-toolchains.sh` (#1021)
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* Cleanup GH issue and PR templates (#1029, #1032)
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* Add support for Ibex core (#979)
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* Add system bus width fragment (#1071)
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* Add support for FSDB waveform files (#1072, #1102)
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* Document simulator timeout settings (#1094)
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* Add FFT Generator (#1067)
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* Add waveforms for post-PNR and power (#1108)
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* Have PRCI control registers use clock of corresponding bus (#1109)
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* Add check to verify that user is running on tagged release (#1114)
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* Hammer tutorial in Sky130 (#1115)
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### Changed
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* Bump CVA6 (#909 )
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* Bump Hammer tutorial for ASAP7 r1p7 (#934)
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* Use Published Chisel, FIRRTL, Treadle, FIRRTLInterpreter packages instead of building from source. #1054
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* Change serialTL width to 32. Speeds up simulations (#1040)
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* Update how sbt flag is overridden (by using `SBT_BIN` variable) (#1041)
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* Use published dependencies for Chisel, FIRRTL, Treadle, and FIRRTLInterpreter (#1054)
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* Split `ConfigFragments.scala` into multiple files (with more organization) (#1061)
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* Avoid initializing nvdla software by default (#1063)
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* Update ASAP to 1.7 in Hammer (#934)
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* Shorten Gemmini docs and point to repo (#1078)
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* Bump Gemmini to 0.6.2 (#1083)
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* Use python2 for tracegen script (#1107)
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* Bump to Chisel/FIRRTL 3.5.1 (#1060, #1113)
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* Bump to FireMarshal 1.12.1 (#1116)
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* Bump to FireSim 1.13.0 (#1118 )
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### Fixed
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* Fix UART portmap for Arty (#968)
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* Support changing make variable `MODEL` from the cmdline (#1030)
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* Force FIRRTL to 1.4.1 (#1052)
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* Fix MMIO IOBinder (#1045)
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* Mask `fd` warning when running make (#1057)
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* Fix Sodor 5-stage hazard check (#1086)
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* Fix Sodor val io issue (#1089)
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* Fix BOOM reference in Readme (#1104)
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* Fix waveforms for post-P&R power analysis (#1108)
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### Removed
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* Remove duplicate `WithUARTIOCells` fragment (#1047)
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* Remove MaxPermSize in java variables (#1082)
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* Remove support for CircleCI (#1105)
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## [1.5.0] - 2021-06-13
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/773
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### Added
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* FireMarshal support for FPGA prototypes (#849)
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* Hammer update to include power estimation flows, rail analysis, hierarchical sim support, and improved ASAP7 plugin with dummy SRAMs (#886)
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* Docker image
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* Support specifying architecture when building tools. (#802)
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* Add Config fragments: WithMultiRoCCFromBuildRoCC, PMP (#809, #821)
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* Add support for simulating an AXI memory interface over the default TL serial link (#812)
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* Add option to add async queues between chip-serialIO and harness serdes (#828)
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* Spike support for multiple extensions, and add sha3 spike model to esp-tools (#837, #897)
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* Default generator support for I2C and PWM (#885)
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### Changed
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* Gemmini bump to version 0.5
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* FireSim bump to version 1.12
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* FireMarshal bump to version 1.12
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* Changes default FireSim frequency from 3.2 GHz (dual clock domains) to 1 GHz (single clock domain)
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* Bump pygments from 2.2.0 to 2.7.4 in docs
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* Hammer tutorial example is now a TinyRocketConfig (#886)
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* Sha3 Spike model moved from sha3 repo to esp-isa-sim
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### Fixed
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* Avoid permissions conflict on shared protocjar.webcache (#774)
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* Passing MBus clock frequency to SimDRAM (#790)
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* Fix parsing of --ignore-qemu option (#791)
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* FPGA Prototype - Support Adding Pullup R's to Bringup GPIOs (#806)
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* Use "tile" instead of "core" to assign frequencies in WithTileFrequency config. fragment (#807)
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* Fix IOCell generation for clock and reset to use IOCellKey (#824)
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* Fix TileResetCtrl to be ahead of reset synchronizers (#826)
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* Fix memory alignment in character count RoCC test (#853)
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* Synchronize JTAG reset to JTAG.TCK. (#859)
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* Updates to system requirements scripts (#874)
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* Rocket-dsp-utils integration and cleanup for dsptools (#888)
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### Removed
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* Dummy DCO collateral from Hammer tutorial example (#886)
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## [1.4.0] - 2021-01-19
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/599
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### Added
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* OpenSBI Support (#633)
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* Support for Diplomacy-based clocking (#614, #682)
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* Support for Diplomacy-based IOBinders (#699)
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* Sodor core integration (#648)
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* Simple Divider-Only PLL for Multiclock RTL Simulation (#676)
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* Enable parallel Hammer simulations (#600)
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* OpenRoad nangate45 Hammer backend (#608)
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* Add support for "LBWIF" backing memory through serialized TileLink (#673)
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* Add variable to control FIRRTL logging verbosity (#627)
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* Add RANDOM_SEED variable to set random init for VCS and Verilator simulations (#629)
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* Fast LoadMem support (#635)
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* Multithreaded Verilator (#654)
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* Support for custom Verilator optimization flags (#728)
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* Add config-fragment to use broadcast manager instead of L2 for coherence (#721)
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* Added optional ignore QEMU flag to `build-toolchains.sh` (#709)
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* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719)
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* Experimental support for SBT thin client. Enable with `export ENABLE_SBT_THIN_CLIENT=1` (https://github.com/sbt/sbt/pull/5620) (#719)
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* Helper `make` targets to launch SBT console (`sbt`) and shutdown/start thin server (<start/shutdown>-sbt-server) (#719)
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* Allow users to override `CC` and `CXX` for `build-toolchains.sh` (#739)
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* Support VCU118/Arty local FPGA prototypes through `fpga-shells` (#747)
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* A 16-core LargeBOOM configuration has been added to FireChip to highlight the resource-optimizing platform configurations added to FireSim in firesim/firesim#636 (#756)
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### Changed
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* Bump Chisel to 3.4.1.x (#742, #719, #751)
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* Bump RocketChip to a7b016e (#742, #719)
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* Bump FireSim to 1.11
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* Bump Gemmini to v0.5
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* Bump to SBT 1.4.4 (#719)
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* Split IOBinders into IOBinders and HarnessBinders | punch out clocks to harness for simwidgets and bridges (#670, #674)
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* Have FireSim build recipes use Chipyard configs rather than FireChip configs (#695)
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* FireMarshal boot default to OpenSBI rather than BBL (#633)
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* Override default baud rate for FireChip (#625)
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* DTM only supports HTIF in DMI mode (#672)
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* Unify HTIF implementation between Chipyard and Firesim (#683)
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* Renamed Ariane to CVA6 (#710)
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* `build.sbt` refactoring/fixes for RC/Chisel/Firrtl bump (#719)
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* Use `; x; y; z;` syntax to run multiple SBT commands (#719)
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* CI Improvements: Cleanup `check-commit` printout. Don't transfer `.git` folders. (#750)
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### Fixed
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* Multi-SHA3 configs (#597)
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* Allow dramsim_ini folder to be set at the command line (#598)
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* Emit HTIF Node in device tree (#607)
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* Fixes for AXI4 MMIO and FBus ports (#618)
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* Only punch realistic subset of DebugIO through chiptop | default to JTAG+Serial (#664)
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* IceNet bug fixes (#720)
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* smartelf2hex.sh bug fixes (#677, #693)
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* env.sh zsh compatibility (#705)
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* build-toolchains.sh bug fixes (#745 #739)
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* Bump Dromajo to work with older version of glibc (#709)
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### Removed
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* Support for synchronous ChipTop reset (#703)
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* Split `JAVA_ARGS` into `JAVA_OPTS` and `SBT_OPTS` (#719)
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## [1.3.0] - 2020-05-31
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/500
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### Added
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* A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. (#480)
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* A new BuildSystem key has been added, which by default builds DigitalTop (#480)
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* The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). (#480)
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* IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. (#480)
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* CI now checks documentation changes (#485)
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* Support FireSim multi-clock (#468)
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* Allows make variables to be injected into build system (#499)
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* Various documentation/comment updates (#511,#517,#518,#537,#533,#542,#570,#569)
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* DSPTools documentation and example (#457, #568)
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* Support for no UART configs (#536)
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* Assemble firrtl-test.jar (#551)
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* Add SPI flash configurations (#546)
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* Add Dromajo + FireSim Dromajo simulation support (#523, #553, #560)
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* NVDLA integration (#505, #559, #580)
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* Add support for Hammer Sim (#512,#581,#580,#582)
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### Changed
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* Bump FireSim to version 1.10 (#574,#586)
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* Bump BOOM to version 3.0 (#523, #574,#580)
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* Bump Gemmini to version 0.3 (#575, #579)
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* Bump SPEC17 workload (#504, #574)
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* Bump Hwacha for fixes (#580)
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* Bump SHA3 for Linux 5.7rc3 support (#580)
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* Bump Rocket Chip to commit 1872f5d (including stage/phase compilation) (#503,#544)
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* Bump FireMarshal to version 1.9.0 (#574)
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* Chisel 3.3 and FIRRTL 1.3 (#503,#544)
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* BuildTop now builds a ChipTop dut module in the TestHarness by default (#480)
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* The default for the TOP make variable is now ChipTop (was Top) (#480)
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* Top has been renamed to DigitalTop (#480)
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* Bump libgloss (#508, #516, #580)
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* The default version of Verilator has changed to v4.034 (#547). Since this release adds enhanced support for Verilog timescales, the build detects if Verilator v4.034 or newer is visible in the build environment and sets default timescale flags appropriately.
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* Use Scalatests for FireSim CI (#528)
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* Cleanup Ariane pre-processing (#505)
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* Modify Issue Template to be more explicit (#557)
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* FireChip uses Chipyard generator (#554)
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* Have all non-synthesizeable constructs in test harness (#572)
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### Fixed
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* Aligned esp-tools spike with Gemmini (#509)
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* Fix debug rule in Verilator (#513)
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* Clean up SBT HTTP warnings (#526,#549)
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* Artefacts dropped in FireSim (#534)
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* Working IceNet + TestChipIP Unit Tests (#525)
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* Don't initialize non-existent Midas submodule (#552)
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* Verilator now supports +permissive similar to VCS (#565)
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* Fix direction of IOCell OE (#586)
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### Deprecated
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* N/A
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### Removed
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* Removed MIDAS examples CI (until a better solution that is faster is found) (#589)
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## [1.2.0] - 2020-03-14
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418
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### Added
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* Ring Topology System Bus NoC (#461)
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* Integration of the Ariane core into Chipyard (#448)
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* FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427)
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* Add option to use blackboxed SimDRAM instead of SimAXIMem (#449)
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* Log `init-submodules` script (#433)
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* Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463)
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### Changed
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* Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features
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* IOBinders and BuildTop unification between FireChip and Chipyard (#390)
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* Bump BOOM to version 2.2.4 (#463)
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* Bump Gemmini to version 0.2 (#469)
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* Update to CircleCI 2.1 config. syntax and cleanup CI file (#421)
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* FireMarshal moved from FireSim to Chipyard (#415)
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* Rename config. mixins to config fragments (#451)
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### Fixed
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* `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414)
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* Fix Hetero. BOOM + Rocket + Hwacha config (#413)
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* Fix VCS stdout (#417)
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* Add a git version check to the init scripts and make them work outside of the repo root (#459)
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* Fix generation of env.sh for zsh (#435)
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* GCD example bug (#465)
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### Deprecated
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* N/A
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### Removed
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* N/A
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## [1.1.0] - 2020-01-25
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A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367
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### Added
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* Gemmini generator and config (PR #356 )
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* Coremark + SPEC2017 benchmarks (PR #326, #338, #344)
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* Add Hwacha tests to CI (PR #284)
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* Add Hwacha tests to benchmark and assembly test suites (PR #284)
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* Added Hwacha + Large Boom Config (PR #315)
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* Add multi-core config with a small Rocket core attached on the side (PR #361 )
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* Add UART and Test Harness UART Adapter to all configurations (PR #348)
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* User can specify $RISCV directory in build-toolchains.sh (PR #334)
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* Checksum offload in IceNet (PR #364)
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### Changed
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* Rocketchip bumped to commit [4f0cdea](https://github.com/chipsalliance/rocket-chip/tree/4f0cdea85c8a2b849fd582ccc8497892001d06b0), for chisel version 3.2.0 which includes Async reset support
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* FireSim release 1.8.0
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* FireMarshal release 1.8.0
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* BOOM release 2.2.3 (PR #397)
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* baremetal software toolchains, using libgloss and newlib instead of in-house syscalls.
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* Add toolchain specific `env.sh` (PR #304)
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* `run-binary`-like interface now dumps `.log` (stdout) and `.out` (stderr) files (PR #308)
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* Split the VLSI build dir on type of design (PR #331)
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* Reduce Ctags runtime and only look at scala, C, C++, and Python files (PR #346)
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* Top/Top-level-traits now behave as a configurable generator (PR #347)
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* Test suite makefrag generator includes Hwacha test suites (PR #342)
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### Fixed
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* Fix VLSI makefile requirements for SRAM generation (PR #318)
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* Only filter header files from common simulation files (PR #322)
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* Bump MacroCompiler for bugfixes (PR #332)
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* commit-on-master check has specific behavior based on source branch (PR #345)
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* Makefile filtering of blackbox resource files only omits .h files (PR #322)
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* Parallel make fixed (PR #386 #392)
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### Deprecated
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* No longer need to specify `WithXTop`, default `Top` is a generator for all `Top`s (PR #347)
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### Removed
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* N/A
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## [1.0.0] - 2019-10-19
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### Added
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* This repository used to be "project-template", a template for Chisel-based projects. Through tighter integration of multiple projects from the Berkeley Architecture Research group at UC Berkeley, this repository is re-released as Chipyard - a framework for agile hardware development of RISC-V based Systems-on-Chip.
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