224 lines
9.0 KiB
Makefile
224 lines
9.0 KiB
Makefile
#########################################################################################
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# verilator makefile
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#########################################################################################
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ifeq ($(shell which verilator),)
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$(error Did not find Verilator in PATH. Make sure all requirements are installed)
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endif
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#########################################################################################
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# general path variables
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#########################################################################################
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base_dir=$(abspath ../..)
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sim_dir=$(abspath .)
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#########################################################################################
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# include shared variables
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#########################################################################################
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include $(base_dir)/variables.mk
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#########################################################################################
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# name of simulator (used to generate *.f arguments file)
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#########################################################################################
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sim_name = verilator
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#########################################################################################
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# verilator simulator types and rules
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#########################################################################################
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sim_prefix = simulator
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sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
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sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
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WAVEFORM_FLAG=-v$(sim_out_name).vcd
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# If verilator seed unspecified, verilator uses srand as random seed
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ifdef RANDOM_SEED
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SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
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else
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SEED_FLAG=
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endif
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.PHONY: default debug
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default: $(sim)
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debug: $(sim_debug)
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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include $(base_dir)/common.mk
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#########################################################################################
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# verilator-specific user-interface variables and commands
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#########################################################################################
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HELP_COMPILATION_VARIABLES += \
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" VERILATOR_PROFILE = 'none' if no verilator profiling (default)" \
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" 'all' if full verilator runtime profiling" \
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" 'threads' if runtime thread profiling only" \
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" VERILATOR_THREADS = how many threads the simulator will use (default 1)" \
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" VERILATOR_FST_MODE = enable FST waveform instead of VCD. use with debug build"
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#########################################################################################
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# verilator/cxx binary and flags
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#########################################################################################
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VERILATOR := verilator --cc --exe
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#----------------------------------------------------------------------------------------
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# user configs
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#----------------------------------------------------------------------------------------
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VERILATOR_PROFILE ?= none
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RUNTIME_PROFILING_CFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),-g -pg,)
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RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
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--prof-threads --prof-cfuncs,\
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$(if $(filter $(VERILATOR_PROFILE),threads),\
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--prof-threads,))
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VERILATOR_THREADS ?= 1
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RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all
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VERILATOR_FST_MODE ?= 0
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TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
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--trace,--trace-fst --trace-threads 1)
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TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
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#----------------------------------------------------------------------------------------
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# verilation configuration/optimization
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#----------------------------------------------------------------------------------------
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# we initially had --noassert for performance, but several modules use
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# assertions, including dramsim, so we enable --assert by default
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VERILATOR_OPT_FLAGS := \
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-O3 \
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--x-assign fast \
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--x-initial fast \
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--output-split 10000 \
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--output-split-cfuncs 100
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# default flags added for external IP (cva6/NVDLA)
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VERILOG_IP_VERILATOR_FLAGS := \
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--unroll-count 256 \
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-Wno-PINCONNECTEMPTY \
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-Wno-ASSIGNDLY \
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-Wno-DECLFILENAME \
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-Wno-UNUSED \
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-Wno-UNOPTFLAT \
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-Wno-BLKANDNBLK \
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-Wno-style \
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-Wall
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# normal flags used for chipyard builds (that are incompatible with vlog ip aka cva6/NVDLA)
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CHIPYARD_VERILATOR_FLAGS := \
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--assert
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# options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
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# NOTE: defer the evaluation of this until it is used!
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PLATFORM_OPTS = $(shell \
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if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \
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then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
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else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)
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# Use --timescale to approximate timescale behavior of pre-4.034
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TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }')
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# see: https://github.com/ucb-bar/riscv-mini/issues/31
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MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
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PREPROC_DEFINES := \
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+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
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+define+STOP_COND=\$$c\(\"done_reset\"\)
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VERILATOR_NONCC_OPTS = \
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$(RUNTIME_PROFILING_VFLAGS) \
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$(RUNTIME_THREADS) \
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$(VERILATOR_OPT_FLAGS) \
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$(PLATFORM_OPTS) \
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-Wno-fatal \
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$(TIMESCALE_OPTS) \
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$(MAX_WIDTH_OPTS) \
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$(PREPROC_DEFINES) \
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--top-module $(VLOG_MODEL) \
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--vpi \
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-f $(sim_common_files) \
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$(sim_vsrcs)
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#----------------------------------------------------------------------------------------
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# gcc configuration/optimization
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#----------------------------------------------------------------------------------------
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include $(base_dir)/sims/common-sim-flags.mk
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VERILATOR_CXXFLAGS = \
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$(SIM_CXXFLAGS) \
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$(RUNTIME_PROFILING_CFLAGS) \
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$(TRACING_CFLAGS) \
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-D__STDC_FORMAT_MACROS \
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-DTEST_HARNESS=V$(VLOG_MODEL) \
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-DVERILATOR \
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-include $(build_dir)/$(long_name).plusArgs \
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-include $(build_dir)/verilator.h
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VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
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VERILATOR_CC_OPTS = \
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-CFLAGS "$(VERILATOR_CXXFLAGS)" \
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-LDFLAGS "$(VERILATOR_LDFLAGS)"
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#----------------------------------------------------------------------------------------
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# full verilator+gcc opts
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#----------------------------------------------------------------------------------------
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VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
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#########################################################################################
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# verilator build paths and file names
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#########################################################################################
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model_dir = $(build_dir)/$(long_name)
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model_dir_debug = $(build_dir)/$(long_name).debug
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model_header = $(model_dir)/V$(VLOG_MODEL).h
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model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
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model_mk = $(model_dir)/V$(VLOG_MODEL).mk
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model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
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#########################################################################################
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# build makefile fragment that builds the verilator sim rules
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#########################################################################################
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$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
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rm -rf $(model_dir)
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mkdir -p $(model_dir)
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$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
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touch $@
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$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS)
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rm -rf $(model_dir_debug)
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mkdir -p $(model_dir_debug)
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$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
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touch $@
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#########################################################################################
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# invoke make to make verilator sim rules
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#########################################################################################
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$(sim): $(model_mk) $(dramsim_lib)
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
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$(sim_debug): $(model_mk_debug) $(dramsim_lib)
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
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#########################################################################################
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# create a verilator vpd rule
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#########################################################################################
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.PRECIOUS: $(output_dir)/%.vpd %.vcd
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$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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rm -f $@.vcd && mkfifo $@.vcd
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vcd2vpd $@.vcd $@ > /dev/null &
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(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $<.out) | tee $<.log)
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#########################################################################################
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# general cleanup rules
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#########################################################################################
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.PHONY: clean clean-sim clean-sim-debug
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clean:
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rm -rf $(gen_dir) $(sim_prefix)-*
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clean-sim:
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rm -rf $(model_dir) $(sim)
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clean-sim-debug:
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rm -rf $(model_dir_debug) $(sim_debug)
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