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c2ce173195a03868c5a33fc40129b35e31d41d0f
chipyard/generators
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Albert Magyar c2ce173195 Add Verilog MMIO GCD peripheral example
2019-09-26 01:47:31 -07:00
..
boom @ 7b68d748b6
Bump boom to version which passes ci
2019-08-29 22:53:41 -07:00
example/src/main
Add Verilog MMIO GCD peripheral example
2019-09-26 01:47:31 -07:00
firechip/src
[firechip] Update regfile optimization mixins
2019-09-09 06:45:30 +00:00
hwacha @ ff4605f5d1
Bump hwacha
2019-05-17 18:38:11 -07:00
icenet @ baa40ed85d
make BlockDevice, SerialAdapter, and IceNIC connect to fbus/pbus instead of sbus
2019-08-22 10:42:37 -07:00
rocket-chip @ 50de8a34c1
bump rc/firrtl | bump to temp boom/testchipip
2019-06-28 11:07:41 -07:00
sha3 @ 83dd1955a9
Fix sha3 build-system dependency
2019-09-01 07:11:52 -07:00
sifive-blocks @ 24dd537894
add sifive blocks | add rebar configs for boom
2019-04-19 21:06:32 -07:00
sifive-cache @ 13d0c2f178
add InclusiveCache
2019-07-02 16:58:08 -07:00
testchipip @ aa13f6ccc1
make BlockDevice, SerialAdapter, and IceNIC connect to fbus/pbus instead of sbus
2019-08-22 10:42:37 -07:00
tracegen/src/main/scala
add tracegen project
2019-08-30 11:38:07 -07:00
utilities/src/main
Move System/Subsystem to utilities
2019-08-27 18:05:24 -07:00
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