98 lines
3.8 KiB
Scala
98 lines
3.8 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import math.min
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import org.chipsalliance.cde.config.{Config, Parameters}
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.subsystem.{MasterPortParams}
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import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
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import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import sifive.fpgashells.shell.{DesignKey}
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import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
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import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
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import chipyard.{BuildSystem}
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import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency, VCU118DDR2Size}
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import chipyard.iobinders.{WithGPIOPunchthrough}
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class WithBringupPeripherals extends Config((site, here, up) => {
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case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
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case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L)))
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case PeripheryGPIOKey => {
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if (BringupGPIOs.width > 0) {
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require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
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val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000))
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val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32)
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List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => {
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GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport))
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})
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}
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else {
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List.empty[GPIOParams]
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}
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}
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case TSIClockMaxFrequencyKey => 100
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case PeripheryTSIHostKey => List(
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TSIHostParams(
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offchipSerialIfWidth = 4,
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mmioBaseAddress = BigInt(0x64006000),
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mmioSourceId = 1 << 13, // manager source
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serdesParams = TSIHostSerdesParams(
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clientPortParams = TLMasterPortParameters.v1(
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clients = Seq(TLMasterParameters.v1(
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name = "tl-tsi-host-serdes",
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sourceId = IdRange(0, (1 << 13))))),
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managerPortParams = TLSlavePortParameters.v1(
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managers = Seq(TLSlaveParameters.v1(
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address = Seq(AddressSet(0, BigInt("FFFFFFFF", 16))), // access everything on chip
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsGet = TransferSizes(1, 64),
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supportsPutFull = TransferSizes(1, 64),
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supportsPutPartial = TransferSizes(1, 64),
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supportsAcquireT = TransferSizes(1, 64),
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supportsAcquireB = TransferSizes(1, 64),
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supportsArithmetic = TransferSizes(1, 64),
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supportsLogical = TransferSizes(1, 64))),
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endSinkId = 1 << 6, // manager sink
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beatBytes = 8)),
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targetMasterPortParams = MasterPortParams(
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base = BigInt("80000000", 16),
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size = site(VCU118DDR2Size),
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beatBytes = 8, // comes from test chip
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idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG
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))
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})
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class WithBringupVCU118System extends Config((site, here, up) => {
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case BuildSystem => (p: Parameters) => new BringupVCU118DigitalTop()(p) // use the VCU118-extended bringup digital top
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})
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class WithBringupAdditions extends Config(
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new WithBringupUART ++
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new WithBringupI2C ++
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new WithBringupGPIO ++
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new WithBringupTSIHost ++
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new WithTSITLIOPassthrough ++
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new WithGPIOPunchthrough ++
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new WithBringupPeripherals ++
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new WithBringupVCU118System)
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class RocketBringupConfig extends Config(
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new WithBringupAdditions ++
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new WithVCU118Tweaks ++
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new chipyard.RocketConfig)
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class BoomBringupConfig extends Config(
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new WithFPGAFrequency(50) ++
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new WithBringupAdditions ++
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new WithVCU118Tweaks ++
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new chipyard.MegaBoomConfig)
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