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Bump fpga-platforms to new organized testchipip

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This commit is contained in:
Jerry Zhao
2023-12-19 12:17:00 -08:00
parent 1e5ebf192a
commit 604cb6358f
17 changed files with 19 additions and 22 deletions
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2
docs/Customization/Memory-Hierarchy.rst
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@@ -94,7 +94,7 @@ memory channel.
Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
and remove the off-chip link. This is done by adding a fragment like
``testchipip.WithScratchpad`` to your configuration and removing the
``testchipip.soc.WithScratchpad`` to your configuration and removing the
memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.
.. literalinclude:: ../../generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala

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fpga/bootrom.rv32.img Executable file
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fpga/bootrom.rv64.img Executable file
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4
fpga/src/main/scala/arty/Configs.scala
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@@ -11,7 +11,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -30,7 +30,7 @@ class WithArtyTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new testchipip.WithNoSerialTL
new testchipip.serdes.WithNoSerialTL
)
class TinyRocketArtyConfig extends Config(

6
fpga/src/main/scala/arty100t/Configs.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -25,7 +25,7 @@ class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
new WithArty100TUARTTSI ++
new WithArty100TDDRTL ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
@@ -56,5 +56,5 @@ class NoCoresArty100TConfig extends Config(
class BringupArty100TConfig extends Config(
new WithArty100TSerialTLToGPIO ++
new WithArty100TTweaks(freqMHz = 50) ++
new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new testchipip.serdes.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
new chipyard.ChipBringupHostConfig)

2
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -20,8 +20,6 @@ import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import testchipip._
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]

6
fpga/src/main/scala/nexysvideo/Configs.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.tile._
import sifive.blocks.devices.uart._
import sifive.fpgashells.shell.{DesignKey}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem}
@@ -26,7 +26,7 @@ class WithNexysVideoTweaks extends Config(
new WithNexysVideoUARTTSI ++
new WithNexysVideoDDRTL ++
new WithNoDesignKey ++
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
@@ -53,7 +53,7 @@ class WithTinyNexysVideoTweaks extends Config(
new WithNexysVideoUARTTSI ++
new WithNoDesignKey ++
new sifive.fpgashells.shell.xilinx.WithNoNexysVideoShellDDR ++ // no DDR
new testchipip.WithUARTTSIClient ++
new testchipip.tsi.WithUARTTSIClient ++
new chipyard.harness.WithSerialTLTiedOff ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++

2
fpga/src/main/scala/nexysvideo/HarnessBinders.scala
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@@ -12,8 +12,6 @@ import sifive.blocks.devices.uart.{UARTParams}
import chipyard._
import chipyard.harness._
import testchipip._
import chipyard.iobinders._
class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({

2
fpga/src/main/scala/vc707/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard.{BuildSystem, ExtTLMem}
import chipyard.harness._

2
fpga/src/main/scala/vcu118/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{SerialTLKey}
import testchipip.serdes.{SerialTLKey}
import chipyard._
import chipyard.harness._

2
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -15,7 +15,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import testchipip.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import testchipip.tsi.{PeripheryTSIHostKey, TSIHostParams, TSIHostSerdesParams}
import chipyard.{BuildSystem}

2
fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
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@@ -13,7 +13,7 @@ import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import sifive.fpgashells.devices.xilinx.xilinxvcu118mig.{XilinxVCU118MIGPads, XilinxVCU118MIGParams, XilinxVCU118MIG}
import testchipip.{TSIHostWidgetIO}
import testchipip.tsi.{TSIHostWidgetIO}
import chipyard.fpga.vcu118.{FMCPMap}

2
fpga/src/main/scala/vcu118/bringup/DigitalTop.scala
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@@ -17,7 +17,7 @@ import chipyard.{DigitalTop, DigitalTopModule}
class BringupVCU118DigitalTop(implicit p: Parameters) extends DigitalTop
with sifive.blocks.devices.i2c.HasPeripheryI2C
with testchipip.HasPeripheryTSIHostWidget
with testchipip.tsi.HasPeripheryTSIHostWidget
{
override lazy val module = new BringupVCU118DigitalTopModule(this)
}

2
fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
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@@ -11,7 +11,7 @@ import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.harness._
import chipyard.iobinders._

2
fpga/src/main/scala/vcu118/bringup/IOBinders.scala
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@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink.{TLBundle}
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp}
import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import testchipip.tsi.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
import chipyard.iobinders.{OverrideIOBinder, Port, TLMemPort}

3
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
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@@ -16,7 +16,8 @@ import sifive.blocks.devices.spi._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio._
import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
import testchipip.util.{TLSinkSetter}
import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}

2
variables.mk
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@@ -97,7 +97,7 @@ ifeq ($(SUB_PROJECT),testchipip)
VLOG_MODEL ?= $(MODEL)
MODEL_PACKAGE ?= chipyard.unittest
CONFIG ?= TestChipUnitTestConfig
CONFIG_PACKAGE ?= testchipip
CONFIG_PACKAGE ?= testchipip.test
GENERATOR_PACKAGE ?= chipyard
TB ?= TestDriver
TOP ?= UnitTestSuite