85b555dbce
* [nvdla] initial nvdla integration * [nvdla] add firesim configs * [nvdla] re-add accidentally deleted line * [nvdla] works on master with small * [nvdla] use master branch of nvdla * [nvdla] remove extra sources * [nvdla] bump * [nvdla + ariane] bump and use insert-includes for pre-processing * [nvdla] add ci | remove target configs in FireChip | update naming * [nvdla] bump nvdla | fix ci run-tests error * [nvdla] re-enable PCWM-L error | fix/update makefile(s) * [nvdla] bump nvdla fragments in FireChip * [misc] bump tutorial patches * [chipyard] remove extra import * [nvdla] bump nvdla for pbus [ci skip] * [nvdla] update firemarshal and add nvdla workload * [nvdla] bump nvdla-workload * [nvdla] bump hw * [docs] add basic documentation * [docs] adjustments to documentation * [misc] update docs | bump firesim with recipe * [misc] disable error on warnings in verilator | bump number width to match RC * [docs] fix doc build error * [verilator] move no fail on warning to be global * [ci skip] [nvdla] bump submodule urls * [misc] move firesim specific configs into nvdla dir [ci skip] * [nvdla] fix run-tests in ci * update RC configs | bump marshal | bump nvdla-workload * [nvdla] bump nvdla-workload [ci skip] * add topology mixin to nvdla configs * update tutorial patches
69 lines
4.2 KiB
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69 lines
4.2 KiB
Markdown
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# Chipyard Framework [](https://circleci.com/gh/ucb-bar/chipyard/tree/master)
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## Using Chipyard
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To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/
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## What is Chipyard
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Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
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It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
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Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
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Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
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Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].
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## Resources
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* Chipyard Documentation: https://chipyard.readthedocs.io/
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* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf
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* Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf
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## Need help?
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* Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
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* If you find a bug, post an issue on this repo
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## Contributing
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* See [CONTRIBUTING.md](/CONTRIBUTING.md)
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## Chipyard-related Publications
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These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.
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* **Generators**
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* **Rocket Chip**: K. Asanovic, et al., *UCB EECS TR*. [PDF](http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-17.pdf).
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* **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://www.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
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* **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
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* **Gemmini**: H. Genc, et al., *arXiv*. [PDF](https://arxiv.org/pdf/1911.09925).
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* **Sims**
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* **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
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* **FireSim Micro Top Picks**: S. Karandikar, et al., *IEEE Micro, Top Picks 2018*. [PDF](https://sagark.org/assets/pubs/firesim-micro-top-picks2018.pdf).
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* **FASED**: D. Biancolin, et al., *FPGA'19*. [PDF](https://people.eecs.berkeley.edu/~biancolin/papers/fased-fpga19.pdf).
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* **Golden Gate**: A. Magyar, et al., *ICCAD'19*. [PDF](https://davidbiancolin.github.io/papers/goldengate-iccad19.pdf).
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* **FirePerf**: S. Karandikar, et al., *ASPLOS'20*. [PDF](https://sagark.org/assets/pubs/fireperf-asplos2020.pdf).
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* **Tools**
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* **Chisel**: J. Bachrach, et al., *DAC'12*. [PDF](https://people.eecs.berkeley.edu/~krste/papers/chisel-dac2012.pdf).
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* **FIRRTL**: A. Izraelevitz, et al., *ICCAD'17*. [PDF](https://ieeexplore.ieee.org/document/8203780).
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* **Chisel DSP**: A. Wang, et al., *DAC'18*. [PDF](https://ieeexplore.ieee.org/document/8465790).
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* **VLSI**
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* **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html).
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[hwacha]:http://hwacha.org
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[hammer]:https://github.com/ucb-bar/hammer
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[firesim]:https://fires.im
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[ucb-bar]: http://bar.eecs.berkeley.edu
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[eecs]: https://eecs.berkeley.edu
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[berkeley]: https://berkeley.edu
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[riscv]: https://riscv.org/
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[rocket-chip]: https://github.com/freechipsproject/rocket-chip
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[boom]: https://github.com/ucb-bar/riscv-boom
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[firemarshal]: https://github.com/firesim/FireMarshal/
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[ariane]: https://github.com/pulp-platform/ariane/
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[gemmini]: https://github.com/ucb-bar/gemmini
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[nvdla]: http://nvdla.org/
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