d97afcdfbc
bug using verilator, make the whitespace consistend in Makefrag-verilator, explicitly name the verilog sources to match vsim, and update verisim/Makefile to use the new source variable names
88 lines
2.6 KiB
Makefile
88 lines
2.6 KiB
Makefile
base_dir=$(abspath ..)
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sim_dir=$(abspath .)
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PROJECT ?= example
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MODEL ?= TestHarness
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CONFIG ?= DefaultExampleConfig
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CFG_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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TOP ?= ExampleTop
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sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
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sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
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default: $(sim)
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debug: $(sim_debug)
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CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
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LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
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include $(base_dir)/Makefrag
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include $(sim_dir)/Makefrag-verilator
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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sim_vsrcs = \
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$(VERILOG_FILE) \
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$(HARNESS_FILE) \
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$(SMEMS_FILE) \
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$(rocketchip_vsrc_dir)/AsyncResetReg.v \
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$(rocketchip_vsrc_dir)/plusarg_reader.v \
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$(testchip_vsrcs)
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sim_csrcs = \
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$(sim_dir)/csrc/verilator-harness.cc \
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$(testchip_csrcs)
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model_dir = $(build_dir)/$(long_name)
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model_dir_debug = $(build_dir)/$(long_name).debug
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model_header = $(model_dir)/V$(MODEL).h
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model_header_debug = $(model_dir_debug)/V$(MODEL).h
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model_mk = $(model_dir)/V$(MODEL).mk
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model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
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$(model_mk): $(sim_vsrcs) $(INSTALLED_VERILATOR)
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rm -rf $(build_dir)/$(long_name)
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mkdir -p $(build_dir)/$(long_name)
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
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-o $(sim) $(sim_vsrcs) $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(build_dir) -include $(model_header)"
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touch $@
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$(sim): $(model_mk) $(sim_csrcs)
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
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$(model_mk_debug): $(sim_vsrcs) $(INSTALLED_VERILATOR)
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mkdir -p $(build_dir)/$(long_name).debug
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$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
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-o $(sim_debug) $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
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-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
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touch $@
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$(sim_debug): $(model_mk_debug) $(sim_csrcs)
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$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
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$(output_dir)/%.out: $(output_dir)/% $(sim)
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$(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
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$(output_dir)/%.run: $(output_dir)/% $(sim)
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$(sim) +max-cycles=1000000 $< && touch $@
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$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
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rm -f $@.vcd && mkfifo $@.vcd
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vcd2vpd $@.vcd $@ > /dev/null &
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$(sim_debug) -v$@.vcd +max-cycles=1000000 $<
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run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
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run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
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run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
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clean:
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rm -rf generated-src ./simulator-*
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