John Wright d97afcdfbc Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a ...

bug using verilator, make the whitespace consistend in
Makefrag-verilator, explicitly name the verilog sources to match vsim,
and update verisim/Makefile to use the new source variable names

2019-02-13 21:13:08 -08:00

..

csrc

verisim: Add verilator-harness.cc from testchipip/csrc

2018-10-05 09:24:35 -07:00

.gitignore

change up gitignore rules

2017-02-07 17:37:26 -08:00

Makefile

Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a

2019-02-13 21:13:08 -08:00

Makefrag-verilator

Bump barstools to fix a bug in MacroCompiler, bump testchipip to fix a

2019-02-13 21:13:08 -08:00