David Biancolin b303cf6e81 Rocket Chip Stage/Phase Bump (#503) ...

[WIP] Minimally elaborating design

Bring up a feature-complete Chipyard stage

Pull in Makefrag generation; Bump submodules

Update config generation, and global reset scheme

Bump submodules; clean up

Bump FireSim

Remove some unhygenic comments / WS

Remove the rocketchip subproject

[CI] Lengthen ariane tests timeout

Address some remaining reviewer comments

[firechip] Refresh a Field that cannot be used across repeated instantiations

Bump all submodules

2020-04-18 17:54:27 +00:00

..

axe @ 4a7cf86960

Fix tracegen target and add to CI

2019-10-21 09:55:40 -07:00

barstools @ e230e8cf3f

Rocket Chip Stage/Phase Bump (#503)

2020-04-18 17:54:27 +00:00

chisel3 @ 7a343dce95

Rocket Chip Stage/Phase Bump (#503)

2020-04-18 17:54:27 +00:00

chisel-testers @ f410c59316

Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358)

2019-12-12 13:39:09 -08:00

DRAMSim2 @ 2ec7965b2e

use blackboxed SimDRAM instead of SimAXIMem

2020-03-02 20:49:20 -08:00

dsptools @ 15145ab623

Add dsptools.

2019-08-02 15:09:22 -07:00

firrtl @ eb637777e3

Rocket Chip Stage/Phase Bump (#503)

2020-04-18 17:54:27 +00:00

firrtl-interpreter @ a881c07df6

make firrtl-interpreter a submodule instead of depending on external snapshot

2019-09-12 00:19:55 +08:00

torture @ 59b0f0f224

added boom and torture | added csmith

2019-04-15 10:17:42 -07:00

treadle @ a03b969af1

Add dsptools.

2019-08-02 15:09:22 -07:00