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added unit_test

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This commit is contained in:
Blaise Tine
2020-03-06 10:31:31 -05:00
parent 9f5235dc3d
commit 0816426662
6 changed files with 91 additions and 13 deletions
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8
rtl/VX_cache/VX_bank.v
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@@ -62,7 +62,7 @@ module VX_bank (
reg snrq_hazard_st0;
assign snrq_valid_st0 = !snrq_empty;
VX_generic_queue_ll #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
VX_generic_queue #(.DATAW(32), .SIZE(`SNRQ_SIZE)) snr_queue(
.clk (clk),
.reset (reset),
.push (snp_req),
@@ -82,7 +82,7 @@ module VX_bank (
assign dram_fill_accept = !dfpq_full;
VX_generic_queue_ll #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
VX_generic_queue #(.DATAW(32+(`BANK_LINE_SIZE_WORDS*32)), .SIZE(`DFPQ_SIZE)) dfp_queue(
.clk (clk),
.reset (reset),
.push (dram_fill_rsp),
@@ -385,7 +385,7 @@ module VX_bank (
wire cwbq_full;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
VX_generic_queue_ll #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
VX_generic_queue #(.DATAW( `vx_clog2(`NUMBER_REQUESTS) + 5 + 2 + (`NW_M1+1) + 32), .SIZE(`CWBQ_SIZE)) cwb_queue(
.clk (clk),
.reset (reset),
@@ -425,7 +425,7 @@ module VX_bank (
assign dram_fill_req_addr = addr_st2;
assign dram_wb_req = !dwbq_empty;
VX_generic_queue_ll #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
VX_generic_queue #(.DATAW( 1 + 32 + (`BANK_LINE_SIZE_WORDS * 32) + 1 + 1), .SIZE(`DWBQ_SIZE)) dwb_queue(
.clk (clk),
.reset (reset),

2
rtl/VX_cache/VX_cache_dfq_queue.v
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@@ -33,7 +33,7 @@ module VX_cache_dfq_queue
wire push_qual = dfqq_push && !dfqq_full;
wire pop_qual = dfqq_pop && use_empty && !out_empty && !dfqq_empty;
VX_generic_queue_ll #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
VX_generic_queue #(.DATAW(`NUMBER_BANKS * (1+32)), .SIZE(`DFQQ_SIZE)) dfqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),

2
rtl/VX_cache/VX_cache_req_queue.v
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@@ -69,7 +69,7 @@ module VX_cache_req_queue (
wire push_qual = reqq_push && !reqq_full;
wire pop_qual = reqq_pop && use_empty && !out_empty && !reqq_empty;
VX_generic_queue_ll #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
VX_generic_queue #(.DATAW( (`NUMBER_REQUESTS * (1+32+32)) + 5 + 2 + (`NW_M1+1) + 3 + 3 ), .SIZE(`REQQ_SIZE)) reqq_queue(
.clk (clk),
.reset (reset),
.push (push_qual),

7
rtl/results.txt
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@@ -1,7 +0,0 @@
# Dynamic Instructions: 51711
# of total cycles: 51728
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.00033
# time to simulate: 0 milliseconds
# GRADE: Failed on test: 4294967295

11
rtl/unit_tests/generic_queue/Makefile Normal file
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@@ -0,0 +1,11 @@
all: testbench.iv
testbench.iv: testbench.v
iverilog testbench.v -o testbench.iv -I ../..
run: testbench.iv
! vvp testbench.iv | grep 'ERROR' || false
clean:
rm testbench.iv

74
rtl/unit_tests/generic_queue/testbench.v Normal file
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@@ -0,0 +1,74 @@
`timescale 1ns/1ns
`include "VX_generic_queue_ll.v"
`define check(x, y) if ((x == y) !== 1) if ((x == y) === 0) $error("x=%h, expected=%h", x, y); else $warning("x=%h, expected=%h", x, y)
module testbench();
reg clk;
reg reset;
reg[3:0] in_data;
reg push;
reg pop;
wire io_enq_ready;
wire[3:0] out_data;
wire io_deq_valid;
wire full, empty;
assign io_enq_ready = !full;
assign io_deq_valid = !empty;
VX_generic_queue_ll #(.DATAW(4), .SIZE(4)) dut (
.clk(clk),
.reset(reset),
.in_data(in_data),
.push(push),
.pop(pop),
.out_data(out_data),
.empty(empty),
.full(full));
always begin
#1 clk = !clk;
end
initial begin
$monitor ("%d: clk=%b rst=%b push=%b, pop=%b, din=%h, empty=%b, full=%b, dout=%h", $time, clk, reset, push, pop, in_data, empty, full, out_data);
#0 clk=0; reset=1; in_data=4'hd; push=1; pop=1;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0);
#0 reset=0; in_data=4'ha; pop=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hx); `check(io_deq_valid, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hb;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hc;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hd;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 push=0; pop=1;
#1 `check(io_enq_ready, 0); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hd); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0);
#0 in_data=4'ha; push=1; pop=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 0);
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#0 in_data=4'hb; pop=1;
#1 `check(io_enq_ready, 1); `check(out_data, 4'ha); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
#0 push=0;
#1 `check(io_enq_ready, 1); `check(out_data, 4'hb); `check(io_deq_valid, 1);
#1 `check(io_enq_ready, 1); `check(out_data, 4'hc); `check(io_deq_valid, 0);
#1 $finish;
end
endmodule