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adding empty to index_buffer

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This commit is contained in:
Blaise Tine
2021-03-30 10:15:42 -07:00
parent b33a994f49
commit 16bef8937b
3 changed files with 11 additions and 5 deletions
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3
hw/rtl/VX_fpu_unit.v
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@@ -54,7 +54,8 @@ module VX_fpu_unit #(
.write_data ({fpu_req_if.wid, fpu_req_if.tmask, fpu_req_if.PC, fpu_req_if.rd, fpu_req_if.wb}),
.read_data ({rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb}),
.release_slot (fpuq_pop),
.full (fpuq_full)
.full (fpuq_full),
`UNUSED_PIN (empty)
);
// can accept new request?

3
hw/rtl/VX_lsu_unit.v
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@@ -113,7 +113,8 @@ module VX_lsu_unit #(
.read_data ({rsp_wid, rsp_pc, rsp_rd, rsp_wb, rsp_type, rsp_offset, rsp_is_dup}),
.release_addr (mbuf_raddr),
.release_slot (mbuf_pop),
.full (mbuf_full)
.full (mbuf_full),
`UNUSED_PIN (empty)
);
assign req_sent_all = (&(dcache_req_if.ready | req_sent_mask | ~req_tmask))

10
hw/rtl/libs/VX_index_buffer.v
View File

@@ -18,11 +18,12 @@ module VX_index_buffer #(
input wire [ADDRW-1:0] release_addr,
input wire release_slot,
output wire full
output wire empty,
output wire full
);
reg [SIZE-1:0] free_slots, free_slots_n;
reg [ADDRW-1:0] write_addr_r;
reg full_r;
reg empty_r, full_r;
wire free_valid;
wire [ADDRW-1:0] free_index;
@@ -51,6 +52,7 @@ module VX_index_buffer #(
if (reset) begin
write_addr_r <= ADDRW'(1'b0);
free_slots <= {SIZE{1'b1}};
empty_r <= 1'b1;
full_r <= 1'b0;
end else begin
if (release_slot) begin
@@ -60,6 +62,7 @@ module VX_index_buffer #(
write_addr_r <= free_index;
end
free_slots <= free_slots_n;
empty_r <= (& free_slots_n);
full_r <= ~free_valid;
end
end
@@ -81,6 +84,7 @@ module VX_index_buffer #(
);
assign write_addr = write_addr_r;
assign empty = empty_r;
assign full = full_r;
endmodule