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scope fixes

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This commit is contained in:
Blaise Tine
2020-06-09 20:49:36 -07:00
parent 1688c65050
commit 19f263c772
13 changed files with 113 additions and 41 deletions
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45
driver/opae/vortex.cpp
View File

@@ -74,8 +74,8 @@ static int vx_scope_start(vx_device_h hdevice) {
vx_device_t *device = ((vx_device_t*)hdevice); vx_device_t *device = ((vx_device_t*)hdevice);
// set start delay // set start delay
uint64_t delay = ((0 << 3) | 4); uint64_t delay = 0;
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, delay)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, ((delay << 3) | 4)));
// start execution // start execution
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN));
@@ -110,27 +110,29 @@ static int vx_scope_start(vx_device_h hdevice) {
ofs << "$var reg 2 15 icache_req_tag $end" << std::endl; ofs << "$var reg 2 15 icache_req_tag $end" << std::endl;
ofs << "$var reg 32 16 icache_rsp_data $end" << std::endl; ofs << "$var reg 32 16 icache_rsp_data $end" << std::endl;
ofs << "$var reg 2 17 icache_rsp_tag $end" << std::endl; ofs << "$var reg 2 17 icache_rsp_tag $end" << std::endl;
ofs << "$var reg 2 18 dcache_req_tag $end" << std::endl; ofs << "$var reg 32 18 dcache_req_addr $end" << std::endl;
ofs << "$var reg 2 19 dcache_rsp_tag $end" << std::endl; ofs << "$var reg 2 19 dcache_req_tag $end" << std::endl;
ofs << "$var reg 29 20 dram_req_tag $end" << std::endl; ofs << "$var reg 32 20 dcache_rsp_data $end" << std::endl;
ofs << "$var reg 29 21 dram_rsp_tag $end" << std::endl; ofs << "$var reg 2 21 dcache_rsp_tag $end" << std::endl;
ofs << "$var reg 29 22 dram_req_tag $end" << std::endl;
ofs << "$var reg 29 23 dram_rsp_tag $end" << std::endl;
ofs << "$var reg 2 24 icache_req_warp $end" << std::endl;
ofs << "$var reg 2 25 dcache_req_warp $end" << std::endl;
fwidth += 128; fwidth += 198;
#define IS_PC_SID(x) (x == 14) const int num_signals = 26;
const int num_signals = 22;
uint64_t frame_width, max_frames, data_valid; uint64_t frame_width, max_frames, data_valid;
ofs << "enddefinitions $end" << std::endl; ofs << "enddefinitions $end" << std::endl;
do {
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0));
do {
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid));
if (data_valid) if (data_valid)
break; break;
std::this_thread::sleep_for(std::chrono::milliseconds(1)); std::this_thread::sleep_for(std::chrono::seconds(1));
} while (true); } while (true);
std::cout << "scope trace dump begin..." << std::endl; std::cout << "scope trace dump begin..." << std::endl;
@@ -186,12 +188,7 @@ static int vx_scope_start(vx_device_h hdevice) {
if (signal_offset == signal_width) { if (signal_offset == signal_width) {
signa_data[signal_width] = 0; // string null termination signa_data[signal_width] = 0; // string null termination
int sid = (num_signals - signal_id); ofs << 'b' << signa_data.data() << ' ' << (num_signals - signal_id) << std::endl;
if (IS_PC_SID(sid)) {
ofs << 'b' << signa_data.data() << "00 " << sid << std::endl;
} else {
ofs << 'b' << signa_data.data() << ' ' << sid << std::endl;
}
signal_offset = 0; signal_offset = 0;
++signal_id; ++signal_id;
} }
@@ -228,22 +225,24 @@ static int vx_scope_start(vx_device_h hdevice) {
break; break;
case 15: case 15:
case 17: case 17:
case 18:
case 19: case 19:
case 21:
case 24:
case 25:
print_signal(word, 2); print_signal(word, 2);
break; break;
case 5: case 5:
case 7: case 7:
print_signal(word, 4); print_signal(word, 4);
break; break;
case 20: case 22:
case 21: case 23:
print_signal(word, 29); print_signal(word, 29);
break; break;
case 14: case 14:
print_signal(word, 30);
break;
case 16: case 16:
case 18:
case 20:
print_signal(word, 32); print_signal(word, 32);
break; break;
} }

12
hw/opae/vortex_afu.sv
View File

@@ -804,7 +804,14 @@ end
`SCOPE_ASSIGN(scope_dram_rsp_tag, vx_dram_rsp_tag); `SCOPE_ASSIGN(scope_dram_rsp_tag, vx_dram_rsp_tag);
`SCOPE_ASSIGN(scope_dram_rsp_ready, vx_dram_rsp_ready); `SCOPE_ASSIGN(scope_dram_rsp_ready, vx_dram_rsp_ready);
`STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 147, "oops!") `STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 217, "oops!")
wire force_changed = (scope_icache_req_valid && scope_icache_req_ready)
|| (scope_icache_rsp_valid && scope_icache_rsp_ready)
|| ((| scope_dcache_req_valid) && scope_dcache_req_ready)
|| ((| scope_dcache_rsp_valid) && scope_dcache_rsp_ready)
|| (scope_dram_req_valid && scope_dram_req_ready)
|| (scope_dram_rsp_valid && scope_dram_rsp_ready);
VX_scope #( VX_scope #(
.DATAW ($bits({`SCOPE_SIGNALS_LIST})), .DATAW ($bits({`SCOPE_SIGNALS_LIST})),
@@ -816,6 +823,7 @@ VX_scope #(
.reset (SoftReset), .reset (SoftReset),
.start (vx_reset), .start (vx_reset),
.stop (cmd_run_done), .stop (cmd_run_done),
.changed (force_changed),
.data_in ({`SCOPE_SIGNALS_LIST}), .data_in ({`SCOPE_SIGNALS_LIST}),
.bus_in (csr_scope_cmd), .bus_in (csr_scope_cmd),
.bus_out (csr_scope_data), .bus_out (csr_scope_data),
@@ -833,6 +841,8 @@ Vortex_Socket #() vx_socket (
`SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_FE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (vx_reset), .reset (vx_reset),

1
hw/rtl/VX_alu_unit.v
View File

@@ -13,7 +13,6 @@ module VX_alu_unit (
output reg[31:0] alu_result, output reg[31:0] alu_result,
output reg alu_stall output reg alu_stall
); );
localparam div_pipeline_len = 20; localparam div_pipeline_len = 20;
localparam mul_pipeline_len = 8; localparam mul_pipeline_len = 8;

4
hw/rtl/VX_back_end.v
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@@ -3,6 +3,8 @@
module VX_back_end #( module VX_back_end #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
`SCOPE_SIGNALS_BE_IO
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -68,6 +70,8 @@ module VX_back_end #(
VX_lsu_unit #( VX_lsu_unit #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) lsu_unit ( ) lsu_unit (
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.lsu_req_if (lsu_req_if), .lsu_req_if (lsu_req_if),

40
hw/rtl/VX_define.vh
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@@ -301,14 +301,18 @@
scope_icache_req_tag, \ scope_icache_req_tag, \
scope_icache_rsp_data, \ scope_icache_rsp_data, \
scope_icache_rsp_tag, \ scope_icache_rsp_tag, \
scope_dcache_req_addr, \
scope_dcache_req_tag, \ scope_dcache_req_tag, \
scope_dcache_rsp_data, \
scope_dcache_rsp_tag, \ scope_dcache_rsp_tag, \
scope_dram_req_tag, \ scope_dram_req_tag, \
scope_dram_rsp_tag scope_dram_rsp_tag, \
scope_icache_req_warp, \
scope_dcache_req_warp
`define SCOPE_SIGNALS_DECL \ `define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \ wire scope_icache_req_valid; \
wire [29:0] scope_icache_req_addr; \ wire [31:0] scope_icache_req_addr; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \ wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \ wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \ wire scope_icache_rsp_valid; \
@@ -316,9 +320,11 @@
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \ wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \ wire scope_icache_rsp_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \ wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \
wire [31:0] scope_dcache_req_addr; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \ wire scope_dcache_req_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \ wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \
wire [31:0] scope_dcache_rsp_data; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \ wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \ wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \ wire scope_dram_req_valid; \
@@ -327,12 +333,14 @@
wire scope_dram_rsp_valid; \ wire scope_dram_rsp_valid; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \ wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag; \
wire scope_dram_rsp_ready; \ wire scope_dram_rsp_ready; \
wire scope_schedule_delay; wire scope_schedule_delay; \
wire [1:0] scope_icache_req_warp; \
wire [1:0] scope_dcache_req_warp;
`define SCOPE_SIGNALS_ICACHE_IO \ `define SCOPE_SIGNALS_ICACHE_IO \
/* verilator lint_off UNDRIVEN */ \ /* verilator lint_off UNDRIVEN */ \
output wire scope_icache_req_valid, \ output wire scope_icache_req_valid, \
output wire [29:0] scope_icache_req_addr, \ output wire [31:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \ output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \ output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \ output wire scope_icache_rsp_valid, \
@@ -344,9 +352,11 @@
`define SCOPE_SIGNALS_DCACHE_IO \ `define SCOPE_SIGNALS_DCACHE_IO \
/* verilator lint_off UNDRIVEN */ \ /* verilator lint_off UNDRIVEN */ \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \ output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \
output wire [31:0] scope_dcache_req_addr, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \ output wire scope_dcache_req_ready, \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \ output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \
output wire [31:0] scope_dcache_rsp_data, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \ output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready, \ output wire scope_dcache_rsp_ready, \
/* verilator lint_on UNDRIVEN */ /* verilator lint_on UNDRIVEN */
@@ -366,6 +376,16 @@
output wire scope_schedule_delay, \ output wire scope_schedule_delay, \
/* verilator lint_on UNDRIVEN */ /* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_FE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [1:0] scope_icache_req_warp, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_BE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [1:0] scope_dcache_req_warp, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_ICACHE_ATTACH \ `define SCOPE_SIGNALS_ICACHE_ATTACH \
.scope_icache_req_valid (scope_icache_req_valid), \ .scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_addr (scope_icache_req_addr), \ .scope_icache_req_addr (scope_icache_req_addr), \
@@ -378,9 +398,11 @@
`define SCOPE_SIGNALS_DCACHE_ATTACH \ `define SCOPE_SIGNALS_DCACHE_ATTACH \
.scope_dcache_req_valid (scope_dcache_req_valid), \ .scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_addr (scope_dcache_req_addr), \
.scope_dcache_req_tag (scope_dcache_req_tag), \ .scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \ .scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \ .scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_data (scope_dcache_rsp_data), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \ .scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready), .scope_dcache_rsp_ready (scope_dcache_rsp_ready),
@@ -395,17 +417,27 @@
`define SCOPE_SIGNALS_CORE_ATTACH \ `define SCOPE_SIGNALS_CORE_ATTACH \
.scope_schedule_delay (scope_schedule_delay), .scope_schedule_delay (scope_schedule_delay),
`define SCOPE_SIGNALS_FE_ATTACH \
.scope_icache_req_warp (scope_icache_req_warp),
`define SCOPE_SIGNALS_BE_ATTACH \
.scope_dcache_req_warp (scope_dcache_req_warp),
`define SCOPE_ASSIGN(d,s) assign d = s `define SCOPE_ASSIGN(d,s) assign d = s
`else `else
`define SCOPE_SIGNALS_ICACHE_IO `define SCOPE_SIGNALS_ICACHE_IO
`define SCOPE_SIGNALS_DCACHE_IO `define SCOPE_SIGNALS_DCACHE_IO
`define SCOPE_SIGNALS_DRAM_IO `define SCOPE_SIGNALS_DRAM_IO
`define SCOPE_SIGNALS_CORE_IO `define SCOPE_SIGNALS_CORE_IO
`define SCOPE_SIGNALS_FE_IO
`define SCOPE_SIGNALS_BE_IO
`define SCOPE_SIGNALS_ICACHE_ATTACH `define SCOPE_SIGNALS_ICACHE_ATTACH
`define SCOPE_SIGNALS_DCACHE_ATTACH `define SCOPE_SIGNALS_DCACHE_ATTACH
`define SCOPE_SIGNALS_DRAM_ATTACH `define SCOPE_SIGNALS_DRAM_ATTACH
`define SCOPE_SIGNALS_CORE_ATTACH `define SCOPE_SIGNALS_CORE_ATTACH
`define SCOPE_SIGNALS_FE_ATTACH
`define SCOPE_SIGNALS_BE_ATTACH
`define SCOPE_ASSIGN(d,s) `define SCOPE_ASSIGN(d,s)
`endif `endif

4
hw/rtl/VX_front_end.v
View File

@@ -3,6 +3,8 @@
module VX_front_end #( module VX_front_end #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
`SCOPE_SIGNALS_FE_IO
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -63,6 +65,8 @@ module VX_front_end #(
VX_icache_stage #( VX_icache_stage #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) icache_stage ( ) icache_stage (
`SCOPE_SIGNALS_FE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.total_freeze (total_freeze), .total_freeze (total_freeze),

9
hw/rtl/VX_icache_stage.v
View File

@@ -3,6 +3,8 @@
module VX_icache_stage #( module VX_icache_stage #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
`SCOPE_SIGNALS_FE_IO
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire total_freeze, input wire total_freeze,
@@ -20,11 +22,6 @@ module VX_icache_stage #(
wire valid_inst = (| fe_inst_meta_fi.valid); wire valid_inst = (| fe_inst_meta_fi.valid);
`DEBUG_BEGIN
wire [`ICORE_TAG_WIDTH-1:0] mem_req_tag = icache_req_if.core_req_tag;
wire [`ICORE_TAG_WIDTH-1:0] mem_rsp_tag = icache_rsp_if.core_rsp_tag;
`DEBUG_END
wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr;
wire mrq_full; wire mrq_full;
@@ -48,6 +45,8 @@ module VX_icache_stage #(
.read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num}) .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num})
); );
`SCOPE_ASSIGN(scope_icache_req_warp, fe_inst_meta_fi.warp_num);
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
//-- //--

5
hw/rtl/VX_lsu_unit.v
View File

@@ -3,6 +3,9 @@
module VX_lsu_unit #( module VX_lsu_unit #(
parameter CORE_ID = 0 parameter CORE_ID = 0
) ( ) (
`SCOPE_SIGNALS_BE_IO
input wire clk, input wire clk,
input wire reset, input wire reset,
@@ -49,6 +52,8 @@ module VX_lsu_unit #(
.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
); );
`SCOPE_ASSIGN(scope_dcache_req_warp, use_warp_num);
wire core_req_rw = (use_mem_write != `BYTE_EN_NO); wire core_req_rw = (use_mem_write != `BYTE_EN_NO);
wire [`NUM_THREADS-1:0][4:0] mem_req_offset; wire [`NUM_THREADS-1:0][4:0] mem_req_offset;

8
hw/rtl/VX_pipeline.v
View File

@@ -6,6 +6,8 @@ module VX_pipeline #(
`SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_FE_IO
`SCOPE_SIGNALS_BE_IO
// Clock // Clock
input wire clk, input wire clk,
@@ -56,7 +58,7 @@ module VX_pipeline #(
wire schedule_delay; wire schedule_delay;
`SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid); `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid);
`SCOPE_ASSIGN(scope_icache_req_addr, icache_req_addr); `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_addr, 2'b0});
`SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag); `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag);
`SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready); `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready);
`SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid); `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid);
@@ -65,9 +67,11 @@ module VX_pipeline #(
`SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready); `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready);
`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid); `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid);
`SCOPE_ASSIGN(scope_dcache_req_addr, {dcache_req_addr[0], 2'b0});
`SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_tag); `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_tag);
`SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_ready); `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_ready);
`SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_valid); `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_valid);
`SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_data[0]);
`SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_tag); `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_tag);
`SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_ready); `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_ready);
@@ -117,6 +121,7 @@ module VX_pipeline #(
VX_front_end #( VX_front_end #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) front_end ( ) front_end (
`SCOPE_SIGNALS_FE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.warp_ctl_if (warp_ctl_if), .warp_ctl_if (warp_ctl_if),
@@ -144,6 +149,7 @@ module VX_pipeline #(
VX_back_end #( VX_back_end #(
.CORE_ID(CORE_ID) .CORE_ID(CORE_ID)
) back_end ( ) back_end (
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.schedule_delay (schedule_delay), .schedule_delay (schedule_delay),

4
hw/rtl/Vortex.v
View File

@@ -6,6 +6,8 @@ module Vortex #(
`SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_FE_IO
`SCOPE_SIGNALS_BE_IO
// Clock // Clock
input wire clk, input wire clk,
@@ -170,6 +172,8 @@ module Vortex #(
`SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_FE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),

4
hw/rtl/Vortex_Cluster.v
View File

@@ -6,6 +6,8 @@ module Vortex_Cluster #(
`SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_FE_IO
`SCOPE_SIGNALS_BE_IO
// Clock // Clock
input wire clk, input wire clk,
@@ -113,6 +115,8 @@ module Vortex_Cluster #(
`SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_FE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/Vortex_Socket.v
View File

@@ -4,6 +4,8 @@ module Vortex_Socket (
`SCOPE_SIGNALS_ICACHE_IO `SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO `SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO `SCOPE_SIGNALS_CORE_IO
`SCOPE_SIGNALS_FE_IO
`SCOPE_SIGNALS_BE_IO
// Clock // Clock
input wire clk, input wire clk,
@@ -62,6 +64,8 @@ module Vortex_Socket (
`SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_FE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
@@ -151,6 +155,8 @@ module Vortex_Socket (
`SCOPE_SIGNALS_ICACHE_ATTACH `SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH `SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH `SCOPE_SIGNALS_CORE_ATTACH
`SCOPE_SIGNALS_FE_ATTACH
`SCOPE_SIGNALS_BE_ATTACH
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),

6
hw/rtl/libs/VX_scope.v
View File

@@ -10,6 +10,7 @@ module VX_scope #(
input wire reset, input wire reset,
input wire start, input wire start,
input wire stop, input wire stop,
input wire changed,
input wire [DATAW-1:0] data_in, input wire [DATAW-1:0] data_in,
input wire [BUSW-1:0] bus_in, input wire [BUSW-1:0] bus_in,
output reg [BUSW-1:0] bus_out, output reg [BUSW-1:0] bus_out,
@@ -103,7 +104,6 @@ module VX_scope #(
if (start_wait) begin if (start_wait) begin
delay_cntr <= delay_cntr - 1; delay_cntr <= delay_cntr - 1;
if (1 == delay_cntr) begin if (1 == delay_cntr) begin
$display("%t: scope-state: recording", $time);
start_wait <= 0; start_wait <= 0;
recording <= 1; recording <= 1;
delta <= 0; delta <= 0;
@@ -112,7 +112,8 @@ module VX_scope #(
if (recording) begin if (recording) begin
if (DELTA_ENABLE) begin if (DELTA_ENABLE) begin
if (0 == waddr if (changed
|| (0 == waddr)
|| (trigger_id != prev_id)) begin || (trigger_id != prev_id)) begin
data_store[waddr] <= data_in; data_store[waddr] <= data_in;
delta_store[waddr] <= delta; delta_store[waddr] <= delta;
@@ -129,7 +130,6 @@ module VX_scope #(
if (stop if (stop
|| (waddr == waddr_end)) begin || (waddr == waddr_end)) begin
$display("%t: scope-state: data_valid, waddr=%0d", $time, waddr);
waddr <= waddr; // keep last written address waddr <= waddr; // keep last written address
recording <= 0; recording <= 0;
data_valid <= 1; data_valid <= 1;