Synthesis Compatible

rtl/VX_alu.v

@@ -1,4 +1,3 @@
-
 `include "VX_define.v"
 
 module VX_alu(
@@ -13,6 +12,71 @@ module VX_alu(
 	);
 
 
+		`ifdef SYN_FUNC
+		wire which_in2;
+
+		wire[31:0] ALU_in1;
+		wire[31:0] ALU_in2;
+		wire[63:0] ALU_in1_mult;
+		wire[63:0] ALU_in2_mult;
+		wire[31:0] upper_immed;
+		wire[31:0] div_result;
+		wire[31:0] rem_result;
+
+
+		assign which_in2  = in_rs2_src == `RS2_IMMED;
+
+		assign ALU_in1 = in_1;
+
+		assign ALU_in2 = which_in2 ? in_itype_immed : in_2;
+
+
+		assign upper_immed = {in_upper_immed, {12{1'b0}}};
+
+
+
+		//always @(posedge `MUL) begin
+
+
+		/* verilator lint_off UNUSED */
+
+
+		wire[63:0] alu_in1_signed = {{32{ALU_in1[31]}}, ALU_in1};
+		wire[63:0] alu_in2_signed = {{32{ALU_in2[31]}}, ALU_in2};	
+		assign ALU_in1_mult = (in_alu_op == `MULHU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in1} : alu_in1_signed;
+		assign ALU_in2_mult = (in_alu_op == `MULHU || in_alu_op == `MULHSU || in_alu_op == `DIVU || in_alu_op == `REMU) ? {32'b0, ALU_in2} : alu_in2_signed;
+		wire[63:0] mult_result = ALU_in1_mult * ALU_in2_mult;
+
+		/* verilator lint_on UNUSED */
+
+		always @(in_alu_op or ALU_in1 or ALU_in2) begin
+			case(in_alu_op)
+				`ADD:        out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
+				`SUB:        out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);
+				`SLLA:       out_alu_result = ALU_in1 << ALU_in2[4:0];
+				`SLT:        out_alu_result = ($signed(ALU_in1) < $signed(ALU_in2)) ? 32'h1 : 32'h0;
+				`SLTU:       out_alu_result = ALU_in1 < ALU_in2 ? 32'h1 : 32'h0;
+				`XOR:        out_alu_result = ALU_in1 ^ ALU_in2;
+				`SRL:        out_alu_result = ALU_in1 >> ALU_in2[4:0];						
+				`SRA:        out_alu_result = $signed(ALU_in1)  >>> ALU_in2[4:0];
+				`OR:         out_alu_result = ALU_in1 | ALU_in2;	
+				`AND:        out_alu_result = ALU_in2 & ALU_in1;	
+				`SUBU:       out_alu_result = (ALU_in1 >= ALU_in2) ? 32'h0 : 32'hffffffff;
+				`LUI_ALU:    out_alu_result = upper_immed;
+				`AUIPC_ALU:  out_alu_result = $signed(in_curr_PC) + $signed(upper_immed);
+				`MUL:        out_alu_result = mult_result[31:0];  
+				`MULH:       out_alu_result = mult_result[63:32];
+				`MULHSU:     out_alu_result = mult_result[63:32];
+				`MULHU:      out_alu_result = mult_result[63:32];
+				`DIV:        out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : $signed($signed(ALU_in1) / $signed(ALU_in2));
+				`DIVU:       out_alu_result = (ALU_in2 == 0) ? 32'hffffffff : ALU_in1 / ALU_in2;
+				`REM:        out_alu_result = (ALU_in2 == 0) ? ALU_in1 : $signed($signed(ALU_in1) % $signed(ALU_in2));
+				`REMU:       out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
+				default: out_alu_result = 32'h0;
+			endcase // in_alu_op
+		end
+
+	`else 
 		wire which_in2;
 
 		wire[31:0] ALU_in1;
@@ -69,7 +133,7 @@ module VX_alu(
 				`REMU:       out_alu_result = (ALU_in2 == 0) ? ALU_in1 : ALU_in1 % ALU_in2;
 				default: out_alu_result = 32'h0;
 			endcase // in_alu_op
-		end
-
+		end		
+	`endif
 
 endmodule // VX_alu

rtl/VX_define.v

@@ -1,11 +1,10 @@
+`include "./VX_define_synth.v"
+
+
 
-`define NT 4
 `define NT_M1 (`NT-1)
 
 // NW_M1 is actually log2(NW)
-//`define NW_M1 (4-1)
-
-`define NW 8
 `define NW_M1 (`CLOG2(`NW))
 
 // Uncomment the below line if NW=1
@@ -13,6 +12,7 @@
 
 // `define SYN 1
 //`define ASIC 1
+//`define SYN_FUNC 1
 
 `define NUM_BARRIERS 4
 

rtl/VX_define_synth.v

@@ -0,0 +1,2 @@
+`define NT 4
+`define NW 8