Separated warp and core in preparation for wspawn support.
This commit is contained in:
54
src/core.cpp
54
src/core.cpp
@@ -29,21 +29,45 @@ void Harp::reg_doWrite(Word cpuId, Word regNum) {
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}
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#endif
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Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id) :
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a(a), iDec(d), mem(mem), pc(0), interruptEnable(false), supervisorMode(true),
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activeThreads(1), reg(0), pred(0), shadowReg(a.getNRegs()),
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shadowPReg(a.getNPRegs()), interruptEntry(0), id(id)
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Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id):
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a(a), iDec(d), mem(mem)
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{
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w.push_back(Warp(this));
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// TODO: core-level initialization
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}
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bool Core::interrupt(Word r0) {
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w[0].interrupt(r0);
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}
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void Core::step() {
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for (unsigned i = 0; i < w.size(); ++i)
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w[i].step();
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}
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bool Core::running() const {
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for (unsigned i = 0; i < w.size(); ++i)
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if (!w[i].running()) return false;
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return true;
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}
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Warp::Warp(Core *c, Word id) :
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core(c), pc(0), interruptEnable(false),
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supervisorMode(true), activeThreads(1), reg(0), pred(0),
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shadowReg(core->a.getNRegs()), shadowPReg(core->a.getNPRegs()),
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interruptEntry(0), id(id)
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{
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/* Build the register file. */
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Word regNum(0);
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for (Word j = 0; j < a.getNThds(); ++j) {
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for (Word j = 0; j < core->a.getNThds(); ++j) {
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reg.push_back(vector<Reg<Word> >(0));
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for (Word i = 0; i < a.getNRegs(); ++i) {
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for (Word i = 0; i < core->a.getNRegs(); ++i) {
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reg[j].push_back(Reg<Word>(id, regNum++));
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}
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pred.push_back(vector<Reg<bool> >(0));
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for (Word i = 0; i < a.getNPRegs(); ++i) {
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for (Word i = 0; i < core->a.getNPRegs(); ++i) {
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pred[j].push_back(Reg<bool>(id, regNum++));
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}
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@@ -52,11 +76,11 @@ Core::Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id) :
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}
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/* Set initial register contents. */
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reg[0][0] = (a.getNThds()<<(a.getWordSize()*8 / 2)) | id;
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reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
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}
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void Core::step() {
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Size fetchPos(0), decPos, wordSize(a.getWordSize());
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void Warp::step() {
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Size fetchPos(0), decPos, wordSize(core->a.getWordSize());
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vector<Byte> fetchBuffer(wordSize);
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if (activeThreads == 0) return;
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@@ -73,10 +97,10 @@ void Core::step() {
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fetchMore = false;
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unsigned fetchSize(wordSize - (pc+fetchPos)%wordSize);
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fetchBuffer.resize(fetchPos + fetchSize);
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Word fetched = mem.fetch(pc + fetchPos, supervisorMode);
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Word fetched = core->mem.fetch(pc + fetchPos, supervisorMode);
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writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
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decPos = 0;
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inst = iDec.decode(fetchBuffer, decPos);
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inst = core->iDec.decode(fetchBuffer, decPos);
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} catch (OutOfBytes o) {
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D(3, "Caught OutOfBytes. Fetching more.");
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fetchMore = true;
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@@ -91,9 +115,9 @@ void Core::step() {
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D(3, "0x" << hex << pc << ": " << *inst);
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#ifdef EMU_INSTRUMENTATION
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{ Addr pcPhys(mem.virtToPhys(pc));
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{ Addr pcPhys(core->mem.virtToPhys(pc));
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Harp::OSDomain::osDomain->
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do_inst(0, pc, pcPhys, decPos, mem.getPtr(pcPhys, decPos),
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do_inst(0, pc, pcPhys, decPos, core->mem.getPtr(pcPhys, decPos),
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(enum inst_type)inst->instTable[inst->getOpcode()].iType);
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}
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#endif
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@@ -146,7 +170,7 @@ void Core::step() {
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delete inst;
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}
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bool Core::interrupt(Word r0) {
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bool Warp::interrupt(Word r0) {
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if (!interruptEnable) return false;
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#ifdef EMU_INSTRUMENTATION
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@@ -67,9 +67,27 @@ namespace Harp {
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Word pc;
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};
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class Warp;
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class Core {
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public:
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Core(const ArchDef &a, Decoder &d, MemoryUnit &mem, Word id=0);
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bool interrupt(Word r0);
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bool running() const;
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void step();
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const ArchDef &a;
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Decoder &iDec;
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MemoryUnit &mem;
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std::vector<Warp> w;
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};
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class Warp {
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public:
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Warp(Core *c, Word id=0);
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void step();
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bool interrupt(Word r0);
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bool running() const { return activeThreads; }
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@@ -78,9 +96,7 @@ namespace Harp {
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#endif
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// private:
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const ArchDef a;
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Decoder &iDec;
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MemoryUnit &mem;
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Core *core;
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Word pc, interruptEntry, shadowPc, id;
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Size activeThreads, shadowActiveThreads;
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@@ -9,7 +9,7 @@
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#include "types.h"
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namespace Harp {
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class Core;
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class Warp;
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class Ref;
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static const Size MAX_REG_SOURCES(3);
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@@ -53,7 +53,7 @@ namespace Harp {
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predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false),
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rdestPresent(false), pdestPresent(false), refLiteral(NULL) {}
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void executeOn(Core &core);
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void executeOn(Warp &warp);
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friend std::ostream &operator<<(std::ostream &, Instruction &);
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/* Setters used to "craft" the instruction. */
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@@ -112,7 +112,7 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) {
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return os;
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}
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void Instruction::executeOn(Core &c) {
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void Instruction::executeOn(Warp &c) {
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D(3, "Begin instruction execute.");
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/* If I try to execute a privileged instruction in user mode, throw an
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@@ -135,7 +135,7 @@ void Instruction::executeOn(Core &c) {
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}
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Size nextActiveThreads = c.activeThreads;
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Size wordSz = c.a.getWordSize();
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Size wordSz = c.core->a.getWordSize();
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Word nextPc = c.pc;
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bool sjOnce(true), // Has not yet split or joined once.
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@@ -157,9 +157,9 @@ void Instruction::executeOn(Core &c) {
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break;
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case EI: c.interruptEnable = true;
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break;
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case TLBADD: c.mem.tlbAdd(reg[rsrc[0]], reg[rsrc[1]], reg[rsrc[2]]);
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case TLBADD: c.core->mem.tlbAdd(reg[rsrc[0]], reg[rsrc[1]], reg[rsrc[2]]);
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break;
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case TLBFLUSH: c.mem.tlbFlush();
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case TLBFLUSH: c.core->mem.tlbFlush();
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break;
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case ADD: reg[rdest] = reg[rsrc[0]] + reg[rsrc[1]];
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reg[rdest].trunc(wordSz);
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@@ -253,15 +253,15 @@ void Instruction::executeOn(Core &c) {
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case LD: memAddr = reg[rsrc[0]] + immsrc;
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.mem.virtToPhys(memAddr), 8, true);
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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#endif
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reg[rdest] = c.mem.read(memAddr, c.supervisorMode);
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reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode);
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break;
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case ST: memAddr = reg[rsrc[1]] + immsrc;
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c.mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
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c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
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#ifdef EMU_INSTRUMENTATION
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Harp::OSDomain::osDomain->
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do_mem(0, memAddr, c.mem.virtToPhys(memAddr), 8, true);
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do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
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#endif
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break;
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case LDI: reg[rdest] = immsrc;
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