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update

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This commit is contained in:
Blaise Tine
2020-04-21 17:50:42 -04:00
parent 24c81c4a3a
commit 38f73af627
3 changed files with 2 additions and 2 deletions
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0
hw/rtl/VX_alu.v → hw/rtl/VX_alu_unit.v
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2
hw/rtl/VX_lsu_unit.v
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@@ -1,6 +1,6 @@
`include "VX_define.vh" `include "VX_define.vh"
module VX_lsu ( module VX_lsu_unit (
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire no_slot_mem, input wire no_slot_mem,

2
hw/simulate/simulator.cpp
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@@ -306,7 +306,7 @@ bool Simulator::run() {
int status = 0; int status = 0;
#else #else
// check riscv-tests PASSED/FAILED status // check riscv-tests PASSED/FAILED status
int status = (int)vortex_->Vortex->back_end->wb->last_data_wb & 0xf; int status = (int)vortex_->Vortex->back_end->writeback->last_data_wb & 0xf;
#endif #endif
return (status == 1); return (status == 1);