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RTL code refactoring

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This commit is contained in:
Blaise Tine
2020-04-20 10:21:06 -04:00
parent 0c81a3ae19
commit 45990e391f
4 changed files with 182 additions and 182 deletions
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118
hw/rtl/generic_cache/VX_bank.v
View File

@@ -44,58 +44,58 @@ module VX_bank #(
// Dram knobs
parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
) (
input wire clk,
input wire reset,
input wire clk,
input wire reset,
// Input Core Request
input wire req_ready,
input wire [NUM_REQUESTS-1:0] bank_valids,
input wire [NUM_REQUESTS-1:0][31:0] bank_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] bank_writedata,
input wire [4:0] bank_rd,
input wire [NUM_REQUESTS-1:0][1:0] bank_wb,
input wire [31:0] bank_pc,
input wire [`NW_BITS-1:0] bank_warp_num,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_read,
input wire [NUM_REQUESTS-1:0][2:0] bank_mem_write,
output wire reqq_full,
// Input Core Request
input wire core_req_ready,
input wire [NUM_REQUESTS-1:0] core_req_valids,
input wire [NUM_REQUESTS-1:0][2:0] core_req_read,
input wire [NUM_REQUESTS-1:0][2:0] core_req_write,
input wire [NUM_REQUESTS-1:0][31:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_data,
input wire [4:0] core_req_rd,
input wire [NUM_REQUESTS-1:0][1:0] core_req_wb,
input wire [31:0] core_req_pc,
input wire [`NW_BITS-1:0] core_req_warp_num,
output wire core_req_full,
// Output Core WB
input wire bank_wb_pop,
output wire bank_wb_valid,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] bank_wb_tid,
output wire [4:0] bank_wb_rd,
output wire [1:0] bank_wb_wb,
output wire [`NW_BITS-1:0] bank_wb_warp_num,
output wire [`WORD_SIZE_RNG] bank_wb_data,
output wire [31:0] bank_wb_pc,
output wire [31:0] bank_wb_address,
// Output Core WB
output wire core_rsp_valid,
output wire [`LOG2UP(NUM_REQUESTS)-1:0] core_rsp_tid,
output wire [4:0] core_rsp_rd,
output wire [1:0] core_rsp_wb,
output wire [`NW_BITS-1:0] core_rsp_warp_num,
output wire [`WORD_SIZE_RNG] core_rsp_data,
output wire [31:0] core_rsp_pc,
output wire [31:0] core_rsp_addr,
input wire core_rsp_pop,
// Dram Fill Requests
output wire dram_fill_req_valid,
output wire[31:0] dram_fill_req_addr,
output wire dram_fill_req_is_snp,
input wire dram_fill_req_queue_full,
input wire dram_fill_req_full,
// Dram Fill Response
input wire dram_rsp_valid,
input wire [31:0] dram_rsp_addr,
input wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_rsp_data,
output wire dram_rsp_ready,
input wire dram_fill_rsp_valid,
input wire [31:0] dram_fill_rsp_addr,
input wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_fill_rsp_data,
output wire dram_fill_rsp_ready,
// Dram WB Requests
input wire dram_wb_queue_pop,
// Dram WB Requests
output wire dram_wb_req_valid,
output wire[31:0] dram_wb_req_addr,
output wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data,
output wire [31:0] dram_wb_req_addr,
output wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dram_wb_req_data,
input wire dram_wb_req_pop,
// Snp Request
input wire snp_req_valid,
input wire[31:0] snp_req_addr,
input wire [31:0] snp_req_addr,
output wire snp_req_full,
output wire snp_fwd_valid,
output wire[31:0] snp_fwd_addr,
output wire [31:0] snp_fwd_addr,
input wire snp_fwd_pop
);
@@ -138,7 +138,7 @@ module VX_bank #(
wire[31:0] dfpq_addr_st0;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] dfpq_filldata_st0;
assign dram_rsp_ready = !dfpq_full;
assign dram_fill_rsp_ready = !dfpq_full;
VX_generic_queue_ll #(
.DATAW(32+(`BANK_LINE_WORDS*`WORD_SIZE)),
@@ -146,8 +146,8 @@ module VX_bank #(
) dfp_queue (
.clk (clk),
.reset (reset),
.push (dram_rsp_valid),
.in_data ({dram_rsp_addr, dram_rsp_data}),
.push (dram_fill_rsp_valid),
.in_data ({dram_fill_rsp_addr, dram_fill_rsp_data}),
.pop (dfpq_pop),
.out_data({dfpq_addr_st0, dfpq_filldata_st0}),
.empty (dfpq_empty),
@@ -168,7 +168,7 @@ module VX_bank #(
wire [2:0] reqq_req_mem_write_st0;
wire [31:0] reqq_req_pc_st0;
assign reqq_push = req_ready && (|bank_valids);
assign reqq_push = core_req_ready && (|core_req_valids);
VX_cache_req_queue #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -192,15 +192,15 @@ module VX_bank #(
.reset (reset),
// Enqueue
.reqq_push (reqq_push),
.bank_valids (bank_valids),
.bank_addr (bank_addr),
.bank_writedata (bank_writedata),
.bank_rd (bank_rd),
.bank_pc (bank_pc),
.bank_wb (bank_wb),
.bank_warp_num (bank_warp_num),
.bank_mem_read (bank_mem_read),
.bank_mem_write (bank_mem_write),
.bank_valids (core_req_valids),
.bank_addr (core_req_addr),
.bank_writedata (core_req_data),
.bank_rd (core_req_rd),
.bank_pc (core_req_pc),
.bank_wb (core_req_wb),
.bank_warp_num (core_req_warp_num),
.bank_mem_read (core_req_read),
.bank_mem_write (core_req_write),
// Dequeue
.reqq_pop (reqq_pop),
@@ -215,7 +215,7 @@ module VX_bank #(
.reqq_req_mem_write_st0(reqq_req_mem_write_st0),
.reqq_req_pc_st0 (reqq_req_pc_st0),
.reqq_empty (reqq_empty),
.reqq_full (reqq_full)
.reqq_full (core_req_full)
);
wire mrvq_pop;
@@ -513,14 +513,14 @@ module VX_bank #(
wire invalidate_fill;
// Enqueue to miss reserv if it's a valid miss
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !(should_flush && dwbq_push) && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign miss_add = valid_st2 && !is_snp_st2 && miss_st2 && !mrvq_full && !(should_flush && dwbq_push) && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
assign miss_add_pc = pc_st2;
assign miss_add_addr = addr_st2;
assign miss_add_data = writeword_st2;
assign {miss_add_rd, miss_add_wb, miss_add_warp_num, miss_add_mem_read, miss_add_mem_write, miss_add_tid} = inst_meta_st2;
// Enqueue to CWB Queue
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
wire cwbq_push = (valid_st2 && !miss_st2) && !cwbq_full && !((FUNC_ID == `L2FUNC_ID) && (miss_add_wb == 0)) && !((is_snp_st2 && valid_st2 && ffsq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire [`WORD_SIZE_RNG] cwbq_data = readword_st2;
wire [`LOG2UP(NUM_REQUESTS)-1:0] cwbq_tid = miss_add_tid;
wire [4:0] cwbq_rd = miss_add_rd;
@@ -529,7 +529,7 @@ module VX_bank #(
wire [31:0] cwbq_pc = pc_st2;
wire cwbq_empty;
assign bank_wb_valid = !cwbq_empty;
assign core_rsp_valid = !cwbq_empty;
VX_generic_queue_ll #(
.DATAW( `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS-1+1) + `WORD_SIZE + 32 + 32),
.SIZE(CWBQ_SIZE)
@@ -540,15 +540,15 @@ module VX_bank #(
.push (cwbq_push),
.in_data ({cwbq_tid, cwbq_rd, cwbq_wb, cwbq_warp_num, cwbq_data, cwbq_pc, addr_st2}),
.pop (bank_wb_pop),
.out_data({bank_wb_tid, bank_wb_rd, bank_wb_wb, bank_wb_warp_num, bank_wb_data, bank_wb_pc, bank_wb_address}),
.pop (core_rsp_pop),
.out_data({core_rsp_tid, core_rsp_rd, core_rsp_wb, core_rsp_warp_num, core_rsp_data, core_rsp_pc, core_rsp_addr}),
.empty (cwbq_empty),
.full (cwbq_full)
);
assign should_flush = snoop_state && valid_st2 && (miss_add_mem_write != `NO_MEM_WRITE) && !is_snp_st2 && !is_fill_st2;
// Enqueue to DWB Queue
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign dwbq_push = ((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2 || should_flush) && !dwbq_full && !((is_snp_st2 && valid_st2 && ffsq_full) ||((valid_st2 && !miss_st2) && cwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
wire[31:0] dwbq_req_addr;
wire dwbq_empty;
@@ -561,7 +561,7 @@ module VX_bank #(
assign dwbq_req_addr = {readtag_st2, addr_st2[`LINE_SELECT_ADDR_END:0]} & `BASE_ADDR_MASK;
end
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_queue_full && !is_snp_st2;
wire possible_fill = valid_st2 && miss_st2 && !dram_fill_req_full && !is_snp_st2;
wire[31:0] fill_invalidator_addr = addr_st2 & `BASE_ADDR_MASK;
VX_fill_invalidator #(
@@ -608,7 +608,7 @@ module VX_bank #(
.push (dwbq_push),
.in_data ({dwbq_req_addr, dwbq_req_data}),
.pop (dram_wb_queue_pop),
.pop (dram_wb_req_pop),
.out_data({dram_wb_req_addr, dram_wb_req_data}),
.empty (dwbq_empty),
.full (dwbq_full)
@@ -617,7 +617,7 @@ module VX_bank #(
wire snp_fwd_push;
wire ffsq_empty;
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full));
assign snp_fwd_push = is_snp_st2 && valid_st2 && !ffsq_full && !(((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full));
assign snp_fwd_valid = !ffsq_empty;
VX_generic_queue_ll #(
@@ -634,6 +634,6 @@ module VX_bank #(
.full (ffsq_full)
);
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_queue_full);
assign stall_bank_pipe = (is_snp_st2 && valid_st2 && ffsq_full) || ((valid_st2 && !miss_st2) && cwbq_full) || (((valid_st2 && miss_st2 && dirty_st2) || fill_saw_dirty_st2) && dwbq_full) || (valid_st2 && miss_st2 && mrvq_full) || (valid_st2 && miss_st2 && !invalidate_fill && dram_fill_req_full);
endmodule : VX_bank

238
hw/rtl/generic_cache/VX_cache.v
View File

@@ -64,8 +64,7 @@ module VX_cache #(
input wire [4:0] core_req_rd,
input wire [NUM_REQUESTS-1:0][1:0] core_req_wb,
input wire [`NW_BITS-1:0] core_req_warp_num,
input wire [31:0] core_req_pc,
input wire [31:0] core_req_pc,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
@@ -104,15 +103,16 @@ module VX_cache #(
);
wire [NUM_BANKS-1:0][NUM_REQUESTS-1:0] per_bank_valids;
wire [NUM_BANKS-1:0] per_bank_wb_pop;
wire [NUM_BANKS-1:0] per_bank_wb_valid;
wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_wb_tid;
wire [NUM_BANKS-1:0][4:0] per_bank_wb_rd;
wire [NUM_BANKS-1:0][1:0] per_bank_wb_wb;
wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num;
wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data;
wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc;
wire [NUM_BANKS-1:0][31:0] per_bank_wb_address;
wire [NUM_BANKS-1:0] per_bank_core_rsp_pop;
wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
wire [NUM_BANKS-1:0][`LOG2UP(NUM_REQUESTS)-1:0] per_bank_core_rsp_tid;
wire [NUM_BANKS-1:0][4:0] per_bank_core_rsp_rd;
wire [NUM_BANKS-1:0][1:0] per_bank_core_rsp_wb;
wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_core_rsp_warp_num;
wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_core_rsp_data;
wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_pc;
wire [NUM_BANKS-1:0][31:0] per_bank_core_rsp_addr;
wire dfqq_full;
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_valid;
@@ -120,7 +120,7 @@ module VX_cache #(
`DEBUG_BEGIN
wire [NUM_BANKS-1:0] per_bank_dram_fill_req_is_snp;
`DEBUG_END
wire [NUM_BANKS-1:0] per_bank_dram_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_fill_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_dram_wb_queue_pop;
wire [NUM_BANKS-1:0] per_bank_dram_wb_req_valid;
@@ -137,8 +137,8 @@ module VX_cache #(
assign core_req_ready = ~(|per_bank_reqq_full);
assign snp_req_full = (|per_bank_snrq_full);
// assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_rsp_ready[0] : per_bank_dram_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]];
assign dram_rsp_ready = (|per_bank_dram_rsp_ready);
// assign dram_rsp_ready = (NUM_BANKS == 1) ? per_bank_dram_fill_rsp_ready[0] : per_bank_dram_fill_rsp_ready[dram_rsp_addr[`BANK_SELECT_ADDR_RNG]];
assign dram_rsp_ready = (|per_bank_dram_fill_rsp_ready);
VX_cache_dram_req_arb #(
.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
@@ -160,20 +160,20 @@ module VX_cache #(
.PRFQ_STRIDE (PRFQ_STRIDE),
.SIMULATED_DRAM_LATENCY_CYCLES (SIMULATED_DRAM_LATENCY_CYCLES)
) cache_dram_req_arb (
.clk (clk),
.reset (reset),
.dfqq_full (dfqq_full),
.per_bank_dram_fill_req_valid(per_bank_dram_fill_req_valid),
.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_ready (dram_req_ready)
.clk (clk),
.reset (reset),
.dfqq_full (dfqq_full),
.per_bank_dram_fill_req_valid (per_bank_dram_fill_req_valid),
.per_bank_dram_fill_req_addr (per_bank_dram_fill_req_addr),
.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
.per_bank_dram_wb_req_valid (per_bank_dram_wb_req_valid),
.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_ready (dram_req_ready)
);
VX_cache_core_req_bank_sel #(
@@ -218,15 +218,15 @@ module VX_cache #(
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) cache_core_rsp_sel_merge (
.per_bank_wb_valid (per_bank_wb_valid),
.per_bank_wb_tid (per_bank_wb_tid),
.per_bank_wb_rd (per_bank_wb_rd),
.per_bank_wb_pc (per_bank_wb_pc),
.per_bank_wb_wb (per_bank_wb_wb),
.per_bank_wb_warp_num(per_bank_wb_warp_num),
.per_bank_wb_data (per_bank_wb_data),
.per_bank_wb_pop (per_bank_wb_pop),
.per_bank_wb_address (per_bank_wb_address),
.per_bank_wb_valid (per_bank_core_rsp_valid),
.per_bank_wb_tid (per_bank_core_rsp_tid),
.per_bank_wb_rd (per_bank_core_rsp_rd),
.per_bank_wb_pc (per_bank_core_rsp_pc),
.per_bank_wb_wb (per_bank_core_rsp_wb),
.per_bank_wb_warp_num(per_bank_core_rsp_warp_num),
.per_bank_wb_data (per_bank_core_rsp_data),
.per_bank_wb_pop (per_bank_core_rsp_pop),
.per_bank_wb_addr (per_bank_core_rsp_addr),
.core_rsp_ready (core_rsp_ready),
.core_rsp_valid (core_rsp_valid),
@@ -255,37 +255,37 @@ module VX_cache #(
genvar curr_bank;
generate
for (curr_bank = 0; curr_bank < NUM_BANKS; curr_bank=curr_bank+1) begin
wire [NUM_REQUESTS-1:0] curr_bank_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata;
wire [4:0] curr_bank_rd;
wire [NUM_REQUESTS-1:0][1:0] curr_bank_wb;
wire [`NW_BITS-1:0] curr_bank_warp_num;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_mem_read;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_mem_write;
wire [31:0] curr_bank_pc;
wire [NUM_REQUESTS-1:0] curr_bank_core_req_valids;
wire [NUM_REQUESTS-1:0][31:0] curr_bank_core_req_addr;
wire [NUM_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_core_req_data;
wire [4:0] curr_bank_core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] curr_bank_core_req_wb;
wire [`NW_BITS-1:0] curr_bank_core_warp_num;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_read;
wire [NUM_REQUESTS-1:0][2:0] curr_bank_core_req_write;
wire [31:0] curr_bank_core_req_pc;
wire curr_bank_wb_pop;
wire curr_bank_wb_valid;
wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_wb_tid;
wire [31:0] curr_bank_wb_pc;
wire [4:0] curr_bank_wb_rd;
wire [1:0] curr_bank_wb_wb;
wire [`NW_BITS-1:0] curr_bank_wb_warp_num;
wire [`WORD_SIZE_RNG] curr_bank_wb_data;
wire [31:0] curr_bank_wb_address;
wire curr_bank_core_rsp_pop;
wire curr_bank_core_rsp_valid;
wire [`LOG2UP(NUM_REQUESTS)-1:0] curr_bank_core_rsp_tid;
wire [31:0] curr_bank_core_rsp_pc;
wire [4:0] curr_bank_core_rsp_rd;
wire [1:0] curr_bank_core_rsp_wb;
wire [`NW_BITS-1:0] curr_bank_core_rsp_warp_num;
wire [`WORD_SIZE_RNG] curr_bank_core_rsp_data;
wire [31:0] curr_bank_core_rsp_addr;
wire curr_bank_dram_rsp_valid;
wire [31:0] curr_bank_dram_rsp_addr;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_rsp_data;
wire curr_bank_dram_rsp_ready;
wire curr_bank_dram_fill_rsp_valid;
wire [31:0] curr_bank_dram_fill_rsp_addr;
wire [`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
wire curr_bank_dram_fill_rsp_ready;
wire curr_bank_dfqq_full;
wire curr_bank_dram_fill_req_full;
wire curr_bank_dram_fill_req_valid;
wire curr_bank_dram_fill_req_is_snp;
wire[31:0] curr_bank_dram_fill_req_addr;
wire curr_bank_dram_wb_queue_pop;
wire curr_bank_dram_wb_req_pop;
wire curr_bank_dram_wb_req_valid;
wire[31:0] curr_bank_dram_wb_req_addr;
wire[`BANK_LINE_WORDS-1:0][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
@@ -301,42 +301,42 @@ module VX_cache #(
wire curr_bank_snp_req_full;
// Core Req
assign curr_bank_valids = per_bank_valids[curr_bank];
assign curr_bank_addr = core_req_addr;
assign curr_bank_writedata = core_req_data;
assign curr_bank_rd = core_req_rd;
assign curr_bank_wb = core_req_wb;
assign curr_bank_pc = core_req_pc;
assign curr_bank_warp_num = core_req_warp_num;
assign curr_bank_mem_read = core_req_read;
assign curr_bank_mem_write = core_req_write;
assign curr_bank_core_req_valids = per_bank_valids[curr_bank];
assign curr_bank_core_req_addr = core_req_addr;
assign curr_bank_core_req_data = core_req_data;
assign curr_bank_core_req_rd = core_req_rd;
assign curr_bank_core_req_wb = core_req_wb;
assign curr_bank_core_req_pc = core_req_pc;
assign curr_bank_core_warp_num = core_req_warp_num;
assign curr_bank_core_req_read = core_req_read;
assign curr_bank_core_req_write = core_req_write;
assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
// Core WB
assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
assign per_bank_wb_valid [curr_bank] = curr_bank_wb_valid;
assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid;
assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd;
assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb;
assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
assign per_bank_wb_pc [curr_bank] = curr_bank_wb_pc;
assign per_bank_wb_address [curr_bank] = curr_bank_wb_address;
assign curr_bank_core_rsp_pop = per_bank_core_rsp_pop[curr_bank];
assign per_bank_core_rsp_valid [curr_bank] = curr_bank_core_rsp_valid;
assign per_bank_core_rsp_tid [curr_bank] = curr_bank_core_rsp_tid;
assign per_bank_core_rsp_rd [curr_bank] = curr_bank_core_rsp_rd;
assign per_bank_core_rsp_wb [curr_bank] = curr_bank_core_rsp_wb;
assign per_bank_core_rsp_warp_num[curr_bank] = curr_bank_core_rsp_warp_num;
assign per_bank_core_rsp_data [curr_bank] = curr_bank_core_rsp_data;
assign per_bank_core_rsp_pc [curr_bank] = curr_bank_core_rsp_pc;
assign per_bank_core_rsp_addr [curr_bank] = curr_bank_core_rsp_addr;
// Dram fill request
assign curr_bank_dfqq_full = dfqq_full;
assign curr_bank_dram_fill_req_full = dfqq_full;
assign per_bank_dram_fill_req_valid[curr_bank] = curr_bank_dram_fill_req_valid;
assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
assign per_bank_dram_fill_req_is_snp[curr_bank] = curr_bank_dram_fill_req_is_snp;
// Dram fill response
assign curr_bank_dram_rsp_valid = (NUM_BANKS == 1) || (dram_rsp_valid && (curr_bank_dram_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
assign curr_bank_dram_rsp_addr = dram_rsp_addr;
assign curr_bank_dram_rsp_data = dram_rsp_data;
assign per_bank_dram_rsp_ready[curr_bank] = curr_bank_dram_rsp_ready;
assign curr_bank_dram_fill_rsp_valid = (NUM_BANKS == 1) || (dram_rsp_valid && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
assign curr_bank_dram_fill_rsp_addr = dram_rsp_addr;
assign curr_bank_dram_fill_rsp_data = dram_rsp_data;
assign per_bank_dram_fill_rsp_ready[curr_bank] = curr_bank_dram_fill_rsp_ready;
// Dram writeback request
assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign curr_bank_dram_wb_req_pop = per_bank_dram_wb_queue_pop[curr_bank];
assign per_bank_dram_wb_req_valid[curr_bank] = curr_bank_dram_wb_req_valid;
assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
@@ -372,55 +372,55 @@ module VX_cache #(
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
) bank (
.clk (clk),
.reset (reset),
// Core req
.req_ready (core_req_ready),
.bank_valids (curr_bank_valids),
.bank_addr (curr_bank_addr),
.bank_writedata (curr_bank_writedata),
.bank_rd (curr_bank_rd),
.bank_wb (curr_bank_wb),
.bank_pc (curr_bank_pc),
.bank_warp_num (curr_bank_warp_num),
.bank_mem_read (curr_bank_mem_read),
.bank_mem_write (curr_bank_mem_write),
.reqq_full (curr_bank_reqq_full),
.reset (reset),
// Core request
.core_req_valids (curr_bank_core_req_valids),
.core_req_read (curr_bank_core_req_read),
.core_req_write (curr_bank_core_req_write),
.core_req_addr (curr_bank_core_req_addr),
.core_req_data (curr_bank_core_req_data),
.core_req_rd (curr_bank_core_req_rd),
.core_req_wb (curr_bank_core_req_wb),
.core_req_pc (curr_bank_core_req_pc),
.core_req_warp_num (curr_bank_core_warp_num),
.core_req_full (curr_bank_reqq_full),
.core_req_ready (core_req_ready),
// Output core wb
.bank_wb_pop (curr_bank_wb_pop),
.bank_wb_valid (curr_bank_wb_valid),
.bank_wb_tid (curr_bank_wb_tid),
.bank_wb_rd (curr_bank_wb_rd),
.bank_wb_wb (curr_bank_wb_wb),
.bank_wb_warp_num (curr_bank_wb_warp_num),
.bank_wb_data (curr_bank_wb_data),
.bank_wb_pc (curr_bank_wb_pc),
.bank_wb_address (curr_bank_wb_address),
// Core response
.core_rsp_valid (curr_bank_core_rsp_valid),
.core_rsp_tid (curr_bank_core_rsp_tid),
.core_rsp_rd (curr_bank_core_rsp_rd),
.core_rsp_wb (curr_bank_core_rsp_wb),
.core_rsp_warp_num (curr_bank_core_rsp_warp_num),
.core_rsp_data (curr_bank_core_rsp_data),
.core_rsp_pc (curr_bank_core_rsp_pc),
.core_rsp_addr (curr_bank_core_rsp_addr),
.core_rsp_pop (curr_bank_core_rsp_pop),
// Dram fill req
// Dram fill request
.dram_fill_req_valid (curr_bank_dram_fill_req_valid),
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
.dram_fill_req_is_snp (curr_bank_dram_fill_req_is_snp),
.dram_fill_req_queue_full(curr_bank_dfqq_full),
.dram_fill_req_full (curr_bank_dram_fill_req_full),
// Dram fill rsp
.dram_rsp_valid (curr_bank_dram_rsp_valid),
.dram_rsp_addr (curr_bank_dram_rsp_addr),
.dram_rsp_data (curr_bank_dram_rsp_data),
.dram_rsp_ready (curr_bank_dram_rsp_ready),
// Dram fill response
.dram_fill_rsp_valid (curr_bank_dram_fill_rsp_valid),
.dram_fill_rsp_addr (curr_bank_dram_fill_rsp_addr),
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
.dram_fill_rsp_ready (curr_bank_dram_fill_rsp_ready),
// Dram writeback
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
// Dram writeback request
.dram_wb_req_valid (curr_bank_dram_wb_req_valid),
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
.dram_wb_req_data (curr_bank_dram_wb_req_data),
.dram_wb_req_pop (curr_bank_dram_wb_req_pop),
// Snoop Request
// Snoop request
.snp_req_valid (curr_bank_snp_req),
.snp_req_addr (curr_bank_snp_req_addr),
.snp_req_full (curr_bank_snp_req_full),
// Snoop Fwd
// Snoop forwarding
.snp_fwd_valid (curr_bank_snp_fwd),
.snp_fwd_addr (curr_bank_snp_fwd_addr),
.snp_fwd_pop (curr_bank_snp_fwd_pop)

6
hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
View File

@@ -50,7 +50,7 @@ module VX_cache_wb_sel_merge #(
input wire [NUM_BANKS-1:0][`NW_BITS-1:0] per_bank_wb_warp_num,
input wire [NUM_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data,
input wire [NUM_BANKS-1:0][31:0] per_bank_wb_pc,
input wire [NUM_BANKS-1:0][31:0] per_bank_wb_address,
input wire [NUM_BANKS-1:0][31:0] per_bank_wb_addr,
output wire [NUM_BANKS-1:0] per_bank_wb_pop,
// Core Writeback
@@ -107,7 +107,7 @@ module VX_cache_wb_sel_merge #(
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_addr[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;
@@ -123,7 +123,7 @@ module VX_cache_wb_sel_merge #(
core_rsp_valid[per_bank_wb_tid[this_bank]] = 1;
core_rsp_data[per_bank_wb_tid[this_bank]] = per_bank_wb_data[this_bank];
core_rsp_pc[per_bank_wb_tid[this_bank]] = per_bank_wb_pc[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_address[this_bank];
core_rsp_addr[per_bank_wb_tid[this_bank]] = per_bank_wb_addr[this_bank];
per_bank_wb_pop_unqual[this_bank] = 1;
end else begin
per_bank_wb_pop_unqual[this_bank] = 0;

2
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
View File

@@ -13,7 +13,7 @@ interface VX_gpu_dcache_rsp_if #(
wire [4:0] core_rsp_read;
wire [1:0] core_rsp_write;
`IGNORE_WARNINGS_END
//wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_pc;
wire [NUM_REQUESTS-1:0][31:0] core_rsp_data;
wire core_rsp_ready;