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minor update

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This commit is contained in:
Blaise Tine
2021-06-13 10:58:48 -07:00
parent a315d0087d
commit 47c3234659
11 changed files with 39 additions and 109 deletions
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71
hw/rtl/VX_csr_io_arb.v
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@@ -1,71 +0,0 @@
`include "VX_define.vh"
module VX_csr_io_arb (
input wire clk,
input wire reset,
// bus select
input wire select_io_rsp,
// input requets
VX_csr_req_if csr_core_req_if,
VX_csr_io_req_if csr_io_req_if,
// output request
VX_csr_pipe_req_if csr_pipe_req_if,
// input response
VX_commit_if csr_pipe_rsp_if,
// outputs responses
VX_commit_if csr_commit_if,
VX_csr_io_rsp_if csr_io_rsp_if
);
`UNUSED_VAR (clk)
`UNUSED_VAR (reset)
wire [31:0] csr_core_req_data = csr_core_req_if.use_imm ? 32'(csr_core_req_if.rs1) : csr_core_req_if.rs1_data;
// requests
assign csr_pipe_req_if.valid = csr_core_req_if.valid || csr_io_req_if.valid;
assign csr_pipe_req_if.wid = csr_core_req_if.wid;
assign csr_pipe_req_if.tmask = csr_core_req_if.tmask;
assign csr_pipe_req_if.PC = csr_core_req_if.PC;
assign csr_pipe_req_if.op_type = csr_core_req_if.valid ? csr_core_req_if.op_type : (csr_io_req_if.rw ? `CSR_RW : `CSR_RS);
assign csr_pipe_req_if.addr = csr_core_req_if.valid ? csr_core_req_if.addr : csr_io_req_if.addr;
assign csr_pipe_req_if.data = csr_core_req_if.valid ? csr_core_req_data : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
assign csr_pipe_req_if.rd = csr_core_req_if.rd;
assign csr_pipe_req_if.wb = csr_core_req_if.wb;
assign csr_pipe_req_if.is_io = !csr_core_req_if.valid;
// core always takes priority over IO bus
assign csr_core_req_if.ready = csr_pipe_req_if.ready;
assign csr_io_req_if.ready = csr_pipe_req_if.ready && !csr_core_req_if.valid;
// responses
wire csr_io_rsp_ready;
VX_skid_buffer #(
.DATAW (32)
) csr_io_out_buffer (
.clk (clk),
.reset (reset),
.valid_in (csr_pipe_rsp_if.valid & select_io_rsp),
.data_in (csr_pipe_rsp_if.data[0]),
.ready_in (csr_io_rsp_ready),
.valid_out (csr_io_rsp_if.valid),
.data_out (csr_io_rsp_if.data),
.ready_out (csr_io_rsp_if.ready)
);
assign csr_commit_if.valid = csr_pipe_rsp_if.valid & ~select_io_rsp;
assign csr_commit_if.wid = csr_pipe_rsp_if.wid;
assign csr_commit_if.tmask = csr_pipe_rsp_if.tmask;
assign csr_commit_if.PC = csr_pipe_rsp_if.PC;
assign csr_commit_if.rd = csr_pipe_rsp_if.rd;
assign csr_commit_if.wb = csr_pipe_rsp_if.wb;
assign csr_commit_if.eop = csr_pipe_rsp_if.eop;
assign csr_commit_if.data = csr_pipe_rsp_if.data;
assign csr_pipe_rsp_if.ready = select_io_rsp ? csr_io_rsp_ready : csr_commit_if.ready;
endmodule

10
hw/rtl/VX_instr_demux.v
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@@ -39,7 +39,7 @@ module VX_instr_demux (
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `ALU_BITS + `MOD_BITS + 32 + 1 + 1 + `NR_BITS + 1 + `NT_BITS + (2 * `NUM_THREADS * 32)),
.BUFFERED (1)
.USE_FASTREG (1)
) alu_buffer (
.clk (clk),
.reset (reset),
@@ -57,7 +57,7 @@ module VX_instr_demux (
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `LSU_BITS + 32 + `NR_BITS + 1 + (2 * `NUM_THREADS * 32)),
.BUFFERED (1)
.USE_FASTREG (1)
) lsu_buffer (
.clk (clk),
.reset (reset),
@@ -75,7 +75,7 @@ module VX_instr_demux (
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `CSR_BITS + `CSR_ADDR_BITS + `NR_BITS + 1 + 1 + `NR_BITS + 32),
.BUFFERED (1)
.USE_FASTREG (1)
) csr_buffer (
.clk (clk),
.reset (reset),
@@ -94,7 +94,7 @@ module VX_instr_demux (
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + `FPU_BITS + `MOD_BITS + `NR_BITS + 1 + (3 * `NUM_THREADS * 32)),
.BUFFERED (1)
.USE_FASTREG (1)
) fpu_buffer (
.clk (clk),
.reset (reset),
@@ -116,7 +116,7 @@ module VX_instr_demux (
VX_skid_buffer #(
.DATAW (`NW_BITS + `NUM_THREADS + 32 + 32 + `GPU_BITS + `NR_BITS + 1 + (`NUM_THREADS * 32 + 32)),
.BUFFERED (1)
.USE_FASTREG (1)
) gpu_buffer (
.clk (clk),
.reset (reset),

25
hw/rtl/VX_mem_unit.v
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@@ -256,26 +256,19 @@ module VX_mem_unit # (
);
end else begin
// core to D-cache request
for (genvar i = 0; i < `DNUM_REQS; ++i) begin
VX_skid_buffer #(
.DATAW (`DCORE_ADDR_WIDTH + 1 + `DWORD_SIZE + (`DWORD_SIZE*8) + `DCORE_TAG_WIDTH)
) core_req_buf (
.clk (clk),
.reset (reset),
.valid_in (dcache_core_req_if.valid[i]),
.data_in ({dcache_core_req_if.addr[i], dcache_core_req_if.rw[i], dcache_core_req_if.byteen[i], dcache_core_req_if.data[i], dcache_core_req_if.tag[i]}),
.ready_in (dcache_core_req_if.ready[i]),
.valid_out (dcache_req_if.valid[i]),
.data_out ({dcache_req_if.addr[i], dcache_req_if.rw[i], dcache_req_if.byteen[i], dcache_req_if.data[i], dcache_req_if.tag[i]}),
.ready_out (dcache_req_if.ready[i])
);
end
assign dcache_req_if.valid = dcache_core_req_if.valid;
assign dcache_req_if.addr = dcache_core_req_if.addr;
assign dcache_req_if.rw = dcache_core_req_if.rw;
assign dcache_req_if.byteen = dcache_core_req_if.byteen;
assign dcache_req_if.data = dcache_core_req_if.data;
assign dcache_req_if.tag = dcache_core_req_if.tag;
assign dcache_core_req_if.ready = dcache_req_if.ready;
// D-cache to core reponse
assign dcache_core_rsp_if.valid = dcache_rsp_if.valid;
assign dcache_core_rsp_if.tag = dcache_rsp_if.tag;
assign dcache_core_rsp_if.data = dcache_rsp_if.data;
assign dcache_rsp_if.ready = dcache_core_rsp_if.ready;
assign dcache_rsp_if.ready = dcache_core_rsp_if.ready;
end
wire [`DMEM_TAG_WIDTH-1:0] icache_mem_req_tag = `DMEM_TAG_WIDTH'(icache_mem_req_if.tag);
@@ -289,7 +282,7 @@ module VX_mem_unit # (
.ADDR_WIDTH (`DMEM_ADDR_WIDTH),
.TAG_IN_WIDTH (`DMEM_TAG_WIDTH),
.BUFFERED_REQ (1),
.BUFFERED_RSP (0)
.BUFFERED_RSP (1)
) mem_arb (
.clk (clk),
.reset (reset),

2
hw/rtl/cache/VX_bank.v vendored
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@@ -476,7 +476,7 @@ module VX_bank #(
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.BUFFERED (NUM_BANKS == 1)
.USE_FASTREG (NUM_BANKS == 1)
) core_rsp_req (
.clk (clk),
.reset (reset),

4
hw/rtl/cache/VX_cache_core_rsp_merge.v vendored
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@@ -107,7 +107,7 @@ module VX_cache_core_rsp_merge #(
VX_skid_buffer #(
.DATAW (NUM_REQS + CORE_TAG_WIDTH + (NUM_REQS *`WORD_WIDTH)),
.BUFFERED (1)
.USE_FASTREG (1)
) pipe_reg (
.clk (clk),
.reset (reset),
@@ -156,7 +156,7 @@ module VX_cache_core_rsp_merge #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (CORE_TAG_WIDTH + `WORD_WIDTH),
.BUFFERED (1)
.USE_FASTREG (1)
) pipe_reg (
.clk (clk),
.reset (reset),

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -4,7 +4,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter BUFFERED = 0
parameter USE_FASTREG = 0
) (
input wire clk,
input wire reset,
@@ -50,7 +50,7 @@ module VX_skid_buffer #(
end else begin
if (BUFFERED) begin
if (USE_FASTREG) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;

8
hw/syn/opae/Makefile
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@@ -76,16 +76,16 @@ $(FPGA_BUILD_DIR)_4c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_4c
$(FPGA_BUILD_DIR)_8c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_8c
afu_synth_setup -s setup8.cfg $(FPGA_BUILD_DIR)_8c
$(FPGA_BUILD_DIR)_16c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_16c
afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_16c
$(FPGA_BUILD_DIR)_32c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_32c
afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_32c
$(FPGA_BUILD_DIR)_64c/build/dcp.qpf:
afu_synth_setup -s setup.cfg $(FPGA_BUILD_DIR)_64c
afu_synth_setup -s setup16.cfg $(FPGA_BUILD_DIR)_64c
gen-sources-1c:
./gen_sources.sh $(CFLAGS) $(CONFIG1) > sources.txt

7
hw/syn/opae/setup16.cfg Normal file
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@@ -0,0 +1,7 @@
+define+SYNTHESIS
+define+QUARTUS
vortex_afu16.json
QI:vortex_afu.qsf
C:sources.txt

7
hw/syn/opae/setup8.cfg Normal file
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@@ -0,0 +1,7 @@
+define+SYNTHESIS
+define+QUARTUS
vortex_afu8.json
QI:vortex_afu.qsf
C:sources.txt

5
hw/syn/opae/vortex_afu16.json
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@@ -18,10 +18,7 @@
"mmio-status": 18,
"mmio-scope-read": 20,
"mmio-scope-write": 22,
"mmio-csr-core": 24,
"mmio-csr-addr": 26,
"mmio-csr-data": 28,
"mmio-csr-read": 30,
"mmio-dev-caps": 24,
"afu-top-interface":
{

5
hw/syn/opae/vortex_afu8.json
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@@ -18,10 +18,7 @@
"mmio-status": 18,
"mmio-scope-read": 20,
"mmio-scope-write": 22,
"mmio-csr-core": 24,
"mmio-csr-addr": 26,
"mmio-csr-data": 28,
"mmio-csr-read": 30,
"mmio-dev-caps": 24,
"afu-top-interface":
{