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Proper SIMT with fine-grain scheduler implemented

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This commit is contained in:
felsabbagh3
2019-05-10 00:49:54 -07:00
parent 96dac5e1ce
commit 48468ed26a
27 changed files with 6080 additions and 3375 deletions
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17
rtl/VX_context.v
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@@ -4,6 +4,7 @@
module VX_context (
input wire clk,
input wire in_warp,
input wire in_wb_warp,
input wire in_valid[`NT_M1:0],
input wire in_write_register,
input wire[4:0] in_rd,
@@ -20,18 +21,26 @@ module VX_context (
output reg[31:0] out_a_reg_data[`NT_M1:0],
output reg[31:0] out_b_reg_data[`NT_M1:0],
output wire out_clone_stall
output wire out_clone_stall,
output wire[31:0] w0_t0_registers[31:0]
);
reg[5:0] state_stall;
initial begin
state_stall = 0;
end
wire[31:0] rd1_register[`NT_M1:0];
wire[31:0] rd2_register[`NT_M1:0];
/* verilator lint_off UNUSED */
wire[31:0] clone_regsiters[31:0];
/* verilator lint_on UNUSED */
assign w0_t0_registers = clone_regsiters;
VX_register_file vx_register_file_master(
.clk (clk),
.in_warp (in_warp),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
@@ -52,6 +61,7 @@ module VX_context (
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_warp (in_warp),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),
@@ -64,11 +74,10 @@ module VX_context (
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
end
endgenerate
reg[5:0] state_stall = 0;
always @(posedge clk) begin
if ((in_is_clone) && state_stall == 0) begin
state_stall <= 10;

145
rtl/VX_context_slave.v Normal file
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@@ -0,0 +1,145 @@
`include "VX_define.v"
module VX_context_slave (
input wire clk,
input wire in_warp,
input wire in_wb_warp,
input wire in_valid[`NT_M1:0],
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_write_data[`NT_M1:0],
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire[31:0] in_curr_PC,
input wire in_is_clone,
input wire in_is_jal,
input wire in_src1_fwd,
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
input wire in_src2_fwd,
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
input wire[31:0] in_wspawn_regs[31:0],
input wire in_wspawn,
output reg[31:0] out_a_reg_data[`NT_M1:0],
output reg[31:0] out_b_reg_data[`NT_M1:0],
output wire out_clone_stall
);
wire[31:0] rd1_register[`NT_M1:0];
wire[31:0] rd2_register[`NT_M1:0];
/* verilator lint_off UNUSED */
wire[31:0] clone_regsiters[31:0];
/* verilator lint_on UNUSED */
reg[5:0] clone_state_stall = 0;
reg[5:0] wspawn_state_stall = 0;
initial begin
clone_state_stall = 0;
wspawn_state_stall = 0;
end
wire to_wspawn = wspawn_state_stall == 2;
// always @(*) begin
// if (to_wspawn)
// $display("-----> to_wspawn == 1");
// end
VX_register_file_master_slave vx_register_file_master(
.clk (clk),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[0]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[0]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_wspawn (in_wspawn),
.in_to_wspawn (to_wspawn),
.in_wspawn_regs (in_wspawn_regs),
.out_regs (clone_regsiters),
.out_src1_data (rd1_register[0]),
.out_src2_data (rd2_register[0])
);
genvar index;
generate
for (index=1; index < `NT; index=index+1)
begin: gen_code_label
wire to_clone;
assign to_clone = (index == rd1_register[0]) && (clone_state_stall == 1);
VX_register_file_slave vx_register_file_slave(
.clk (clk),
.in_warp (in_warp),
.in_wb_warp (in_wb_warp),
.in_valid (in_valid[index]),
.in_write_register (in_write_register),
.in_rd (in_rd),
.in_data (in_write_data[index]),
.in_src1 (in_src1),
.in_src2 (in_src2),
.in_clone (in_is_clone),
.in_to_clone (to_clone),
.in_regs (clone_regsiters),
.out_src1_data (rd1_register[index]),
.out_src2_data (rd2_register[index])
);
end
endgenerate
// always @(*) begin
// if (in_valid[0] && in_valid[1]) begin
// $display("Reg write: %h %h", in_write_data[0], in_write_data[1]);
// end else if (in_valid[0]) begin
// $display("Reg write: %h", in_write_data[0]);
// end
// end
// for clone
always @(posedge clk) begin
if ((in_is_clone) && clone_state_stall == 0) begin
clone_state_stall <= 10;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
end else if (clone_state_stall == 1) begin
// $display("ENDING CLONE, 1 =? %h = %h -- %d", rd1_register[0], to_clone_1, in_is_clone);
clone_state_stall <= 0;
end else if (clone_state_stall > 0) begin
clone_state_stall <= clone_state_stall - 1;
// $display("CLONEEE BITCH %d, 1 =? %h = %h -- %d", clone_state_stall, rd1_register[0], to_clone_1, in_is_clone);
end
end
// for wspawn
always @(posedge clk) begin
if ((in_wspawn) && wspawn_state_stall == 0) begin
wspawn_state_stall <= 10;
// $display("starting wspawn stalling -- in_wspawn: %d -- stall %d", in_wspawn, wspwan_stall);
end else if (wspawn_state_stall == 1) begin
// $display("ENDING wspawn stalling -- in_wspawn %d -- stall: %d", in_wspawn, wspwan_stall);
wspawn_state_stall <= 0;
end else if (wspawn_state_stall > 0) begin
wspawn_state_stall <= wspawn_state_stall - 1;
// $display("wspawn state: %d in_wspawn: %d -- stall: %d", wspawn_state_stall, in_wspawn, wspwan_stall);
end
end
genvar index_out_reg;
generate
for (index_out_reg = 0; index_out_reg < `NT; index_out_reg = index_out_reg + 1)
begin
assign out_a_reg_data[index_out_reg] = ( (in_is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data[index_out_reg] : rd1_register[index_out_reg]));
assign out_b_reg_data[index_out_reg] = (in_src2_fwd == 1'b1) ? in_src2_fwd_data[index_out_reg] : rd2_register[index_out_reg];
end
endgenerate
wire clone_stall = ((clone_state_stall == 0) && in_is_clone) || ((clone_state_stall != 1) && in_is_clone);
wire wspwan_stall = ((wspawn_state_stall == 0) && in_wspawn) || (wspawn_state_stall > 1);
assign out_clone_stall = clone_stall || wspwan_stall;
endmodule

171
rtl/VX_decode.v
View File

@@ -3,55 +3,55 @@
module VX_decode(
// Fetch Inputs
input wire clk,
input wire[31:0] in_instruction,
input wire[31:0] in_curr_PC,
input wire in_valid[`NT_M1:0],
input wire clk,
input wire[31:0] in_instruction,
input wire[31:0] in_curr_PC,
input wire in_valid[`NT_M1:0],
// WriteBack inputs
input wire[31:0] in_write_data[`NT_M1:0],
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire in_wb_valid[`NT_M1:0],
input wire[`NW_M1:0] in_wb_warp_num,
input wire[31:0] in_write_data[`NT_M1:0],
input wire[4:0] in_rd,
input wire[1:0] in_wb,
input wire in_wb_valid[`NT_M1:0],
input wire[`NW_M1:0] in_wb_warp_num,
// FORWARDING INPUTS
input wire in_src1_fwd,
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
input wire in_src2_fwd,
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
input wire[`NW_M1:0] in_warp_num,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_mask,
input wire in_src1_fwd,
input wire[31:0] in_src1_fwd_data[`NT_M1:0],
input wire in_src2_fwd,
input wire[31:0] in_src2_fwd_data[`NT_M1:0],
input wire[`NW_M1:0] in_warp_num,
output wire[11:0] out_csr_address,
output wire out_is_csr,
output wire[31:0] out_csr_mask,
// Outputs
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[1:0] out_wb,
output wire[4:0] out_alu_op,
output wire out_rs2_src,
output reg[31:0] out_itype_immed,
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output reg[2:0] out_branch_type,
output reg out_branch_stall,
output reg out_jal,
output reg[31:0] out_jal_offset,
output reg[19:0] out_upper_immed,
output wire[31:0] out_PC_next,
output reg out_clone_stall,
output wire out_change_mask,
output wire out_thread_mask[`NT_M1:0],
output wire out_valid[`NT_M1:0],
output wire[`NW_M1:0] out_warp_num
output wire[4:0] out_rd,
output wire[4:0] out_rs1,
output wire[4:0] out_rs2,
output wire[31:0] out_a_reg_data[`NT_M1:0],
output wire[31:0] out_b_reg_data[`NT_M1:0],
output wire[1:0] out_wb,
output wire[4:0] out_alu_op,
output wire out_rs2_src,
output reg[31:0] out_itype_immed,
output wire[2:0] out_mem_read,
output wire[2:0] out_mem_write,
output reg[2:0] out_branch_type,
output reg out_branch_stall,
output reg out_jal,
output reg[31:0] out_jal_offset,
output reg[19:0] out_upper_immed,
output wire[31:0] out_PC_next,
output reg out_clone_stall,
output wire out_change_mask,
output wire out_thread_mask[`NT_M1:0],
output wire out_valid[`NT_M1:0],
output wire[`NW_M1:0] out_warp_num,
output wire out_wspawn,
output wire[31:0] out_wspawn_pc,
output wire out_ebreak
);
wire[6:0] curr_opcode;
@@ -73,6 +73,7 @@ module VX_decode(
wire is_clone;
wire is_jalrs;
wire is_jmprt;
wire is_wspawn;
wire write_register;
@@ -110,11 +111,28 @@ module VX_decode(
reg[4:0] alu_op;
reg[4:0] mul_alu;
wire context_zero_valid = (in_wb_warp_num == 0);
wire[31:0] w0_t0_registers[31:0];
VX_context VX_Context(
wire context_zero_valid = (in_wb_warp_num == 0);
wire[31:0] zero_a_reg_data[`NT_M1:0];
wire[31:0] zero_b_reg_data[`NT_M1:0];
reg zero_clone_stall;
// always @(*) begin
// $display("DECODE WARP: %h", in_warp_num);
// end
wire curr_warp_zero = in_warp_num == 0;
wire curr_warp_one = in_warp_num == 1;
// always @(*) begin
// $display("DECODE WARP: %h PC: %h",in_warp_num, in_curr_PC);
// end
VX_context VX_Context_zero(
.clk (clk),
.in_warp (context_zero_valid),
.in_warp (curr_warp_zero),
.in_wb_warp (context_zero_valid),
.in_valid (in_wb_valid),
.in_rd (in_rd),
.in_src1 (out_rs1),
@@ -128,13 +146,52 @@ module VX_decode(
.in_src2_fwd_data (in_src2_fwd_data),
.in_write_register(write_register),
.in_write_data (in_write_data),
.out_a_reg_data (out_a_reg_data),
.out_b_reg_data (out_b_reg_data),
.out_clone_stall (out_clone_stall)
);
.out_a_reg_data (zero_a_reg_data),
.out_b_reg_data (zero_b_reg_data),
.out_clone_stall (zero_clone_stall),
.w0_t0_registers (w0_t0_registers)
);
wire context_one_valid = (in_wb_warp_num == 1);
wire[31:0] one_a_reg_data[`NT_M1:0];
wire[31:0] one_b_reg_data[`NT_M1:0];
reg one_clone_stall;
VX_context_slave VX_Context_one(
.clk (clk),
.in_warp (curr_warp_one),
.in_wb_warp (context_one_valid),
.in_valid (in_wb_valid),
.in_rd (in_rd),
.in_src1 (out_rs1),
.in_src2 (out_rs2),
.in_curr_PC (in_curr_PC),
.in_is_clone (is_clone),
.in_is_jal (is_jal),
.in_src1_fwd (in_src1_fwd),
.in_src1_fwd_data (in_src1_fwd_data),
.in_src2_fwd (in_src2_fwd),
.in_src2_fwd_data (in_src2_fwd_data),
.in_write_register(write_register),
.in_write_data (in_write_data),
.in_wspawn_regs (w0_t0_registers),
.in_wspawn (is_wspawn),
.out_a_reg_data (one_a_reg_data),
.out_b_reg_data (one_b_reg_data),
.out_clone_stall (one_clone_stall)
);
assign out_a_reg_data = curr_warp_zero ? zero_a_reg_data : one_a_reg_data;
assign out_b_reg_data = curr_warp_zero ? zero_b_reg_data : one_b_reg_data;
assign out_clone_stall = zero_clone_stall || one_clone_stall;
// always @(*) begin
// if (context_one_valid) begin
// $display("PC: %h -> src1: %h\tsrc2: %h",in_curr_PC, one_a_reg_data[0], one_b_reg_data[0]);
// end
// end
assign out_warp_num = in_warp_num;
assign out_valid = in_valid;
assign out_valid = in_valid;
assign write_register = (in_wb != 2'h0) ? (1'b1) : (1'b0);
@@ -171,6 +228,10 @@ module VX_decode(
assign is_clone = is_gpgpu && (func3 == 5);
assign is_jalrs = is_gpgpu && (func3 == 6);
assign is_jmprt = is_gpgpu && (func3 == 4);
assign is_wspawn = is_gpgpu && (func3 == 0);
assign out_wspawn = is_wspawn;
assign out_wspawn_pc = out_a_reg_data[0];
// always @(*) begin
// if (is_jalrs) begin
@@ -259,7 +320,7 @@ module VX_decode(
case(curr_opcode)
`LUI_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3};
`AUIPC_INST: out_upper_immed = {func7, out_rs2, out_rs1, func3};
default: out_upper_immed = 20'h0;
default: out_upper_immed = 20'h0;
endcase // curr_opcode
end
@@ -306,6 +367,7 @@ module VX_decode(
end
`SYS_INST:
begin
// $display("SYS EBREAK %h", (jal_sys_jal && in_valid[0]) );
out_jal = jal_sys_jal && in_valid[0];
out_jal_offset = jal_sys_off;
end
@@ -317,6 +379,13 @@ module VX_decode(
endcase
end
wire is_ebreak;
assign is_ebreak = (curr_opcode == `SYS_INST) && (jal_sys_jal && in_valid[0]);
assign out_ebreak = is_ebreak;
// CSR

7
rtl/VX_execute.v
View File

@@ -68,6 +68,13 @@ module VX_execute (
end
endgenerate
// always @(*) begin
// if ((in_alu_op == `MUL) && (in_warp_num == 1)) begin
// $display("@PC: %h ---> %d * %d = %d\t%d * %d = %d", in_curr_PC, in_a_reg_data[0], in_b_reg_data[0], out_alu_result[0], in_a_reg_data[1], in_b_reg_data[1], out_alu_result[1]);
// end
// end
assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
assign out_jal = in_jal;

128
rtl/VX_fetch.v
View File

@@ -2,30 +2,34 @@
`include "VX_define.v"
module VX_fetch (
input wire clk,
input wire reset,
input wire in_branch_dir,
input wire in_freeze,
input wire[31:0] in_branch_dest,
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
input wire clk,
input wire reset,
input wire in_branch_dir,
input wire in_freeze,
input wire[31:0] in_branch_dest,
input wire in_branch_stall,
input wire in_fwd_stall,
input wire in_branch_stall_exe,
input wire in_clone_stall,
input wire in_jal,
input wire[31:0] in_jal_dest,
input wire in_interrupt,
input wire in_debug,
input wire[31:0] in_instruction,
input wire in_thread_mask[`NT_M1:0],
input wire in_change_mask,
input wire[`NW_M1:0] in_decode_warp_num,
input wire[`NW_M1:0] in_memory_warp_num,
input wire in_wspawn,
input wire[31:0] in_wspawn_pc,
input wire in_ebreak,
output wire[31:0] out_instruction,
output wire out_delay,
output wire[31:0] out_instruction,
output wire out_delay,
output wire[`NW_M1:0] out_warp_num,
output wire[31:0] out_curr_PC,
output wire out_valid[`NT_M1:0]
output wire[31:0] out_curr_PC,
output wire out_valid[`NT_M1:0],
output wire out_ebreak
);
reg stall;
@@ -39,42 +43,98 @@ module VX_fetch (
warp_state = 0;
end
wire add_warp = in_wspawn && !in_ebreak && !in_clone_stall;
wire remove_warp = in_ebreak && !in_wspawn && !in_clone_stall;
always @(posedge clk or posedge reset) begin
if (reset || (warp_num == warp_state)) begin
warp_num <= 0;
if (reset || (warp_num == warp_state) || remove_warp || add_warp) begin
warp_num <= 0;
end else begin
warp_num <= warp_num + 1;
warp_num <= warp_num + 1;
end
if (add_warp) begin
// $display("Adding a new warp %h", warp_state);
warp_state <= warp_state + 1;
end else if (remove_warp) begin
// $display("Removing a warp %h", warp_state);
warp_state <= warp_state - 1;
end
end
assign out_ebreak = (warp_state == 0) && in_ebreak;
assign stall = in_clone_stall || in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || in_freeze || in_debug;
wire[31:0] warp_pc;
wire warp_valid[`NT_M1:0];
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
wire warp_zero_stall = stall || (warp_num == 1);
wire warp_zero_wspawn = 0;
wire[31:0] warp_zero_wspawn_pc = 32'h0;
wire warp_zero_change_mask = in_change_mask && (in_decode_warp_num == 0);
wire warp_zero_jal = in_jal && (in_memory_warp_num == 0);
wire warp_zero_branch = in_branch_dir && (in_memory_warp_num == 0);
VX_warp VX_Warp(
wire[31:0] warp_zero_pc;
wire warp_zero_valid[`NT_M1:0];
VX_warp VX_Warp_zero(
.clk (clk),
.reset (reset),
.stall (stall),
.stall (warp_zero_stall),
.in_thread_mask(in_thread_mask),
.in_change_mask(warp_zero_change_mask),
.in_jal (warp_zero_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (warp_zero_branch),
.in_branch_dest(in_branch_dest),
.out_PC (warp_pc),
.out_valid (warp_valid)
.in_wspawn (warp_zero_wspawn),
.in_wspawn_pc (warp_zero_wspawn_pc),
.out_PC (warp_zero_pc),
.out_valid (warp_zero_valid)
);
assign out_PC = warp_pc;
wire warp_one_change_mask = in_change_mask && (in_decode_warp_num == 1);
wire warp_one_jal = in_jal && (in_memory_warp_num == 1);
wire warp_one_branch = in_branch_dir && (in_memory_warp_num == 1);
wire warp_one_stall = stall || (warp_num == 0);
wire[31:0] warp_one_pc;
wire warp_one_valid[`NT_M1:0];
VX_warp VX_Warp_one(
.clk (clk),
.reset (reset),
.stall (warp_one_stall),
.in_thread_mask(in_thread_mask),
.in_change_mask(warp_one_change_mask),
.in_jal (warp_one_jal),
.in_jal_dest (in_jal_dest),
.in_branch_dir (warp_one_branch),
.in_branch_dest(in_branch_dest),
.in_wspawn (in_wspawn),
.in_wspawn_pc (in_wspawn_pc),
.out_PC (warp_one_pc),
.out_valid (warp_one_valid)
);
// always @(*) begin
// if (in_wspawn) begin
// $display("Spawning a warp @ %h",in_wspawn_pc);
// end
// end
// always @(posedge clk) begin
// $display("curr warp: %h Threads:%d%d PC: %h", warp_num, out_valid[0],out_valid[1], out_PC);
// end
// always @(*) begin
// if (warp_num == 1) begin
// $display("Going to PC: %h", warp_one_pc);
// end
// end
assign out_PC = (warp_num == 0) ? warp_zero_pc : warp_one_pc;
assign out_valid = (warp_num == 0) ? warp_zero_valid : warp_one_valid;
// always @(*) begin
// $display("FETCH PC: %h (%h, %h, %h)",delete, delete, in_jal_dest, in_branch_dest);
@@ -82,9 +142,9 @@ module VX_fetch (
assign out_curr_PC = out_PC;
assign out_valid = warp_valid;
assign out_warp_num = warp_num;
assign out_delay = 0;
assign out_instruction = stall ? 32'b0 : in_instruction;

14
rtl/VX_memory.v
View File

@@ -65,6 +65,12 @@ module VX_memory (
assign out_cache_driver_in_data = in_rd2;
assign out_cache_driver_in_valid = in_valid;
// always @(*) begin
// if (in_valid[0] && (in_mem_write == `SW_MEM_WRITE) && (in_alu_result[0] >= 32'h810049a0)) begin
// $display("SW$ PC: %h - Warp: %h -> [%h]%h = %h || [%h]%h = %h",in_curr_PC, in_warp_num, in_valid[0], in_alu_result[0], in_rd2[0], in_valid[1], in_alu_result[1], in_rd2[1]);
// end
// end
// wire[31:0] sm_out_data[`NT_M1:0];
@@ -113,7 +119,13 @@ module VX_memory (
end
`BLT: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
`BGT: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`BLTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
`BLTU:
begin
out_branch_dir = (in_alu_result[0][31] == 0) ? `NOT_TAKEN : `TAKEN;
if (in_warp_num == 1) begin
// $display("BLTU PC:%h : %d < %d = %d", in_curr_PC, in_rs1, in_rs2, (in_alu_result[0][31] == 0));
end
end
`BGTU: out_branch_dir = (in_alu_result[0][31] == 0) ? `TAKEN : `NOT_TAKEN;
`NO_BRANCH: out_branch_dir = `NOT_TAKEN;
default: out_branch_dir = `NOT_TAKEN;

9
rtl/VX_register_file.v
View File

@@ -2,7 +2,7 @@
module VX_register_file (
input wire clk,
input wire in_warp,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
@@ -30,6 +30,11 @@ module VX_register_file (
// end
// end
// always @(*) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
assign out_regs = registers;
assign write_data = in_data;
@@ -38,7 +43,7 @@ module VX_register_file (
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid;
always @(posedge clk) begin
if(write_enable && in_warp) begin
if(write_enable && in_wb_warp) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end

72
rtl/VX_register_file_master_slave.v Normal file
View File

@@ -0,0 +1,72 @@
module VX_register_file_master_slave (
input wire clk,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
input wire[31:0] in_data,
input wire[4:0] in_src1,
input wire[4:0] in_src2,
input wire in_wspawn,
input wire in_to_wspawn,
input wire[31:0] in_wspawn_regs[31:0],
output reg[31:0] out_src1_data,
output reg[31:0] out_src2_data,
output wire[31:0] out_regs[31:0]
);
reg[31:0] registers[31:0];
wire[31:0] write_data;
wire[4:0] write_register;
wire write_enable;
assign out_regs = registers;
// reg[5:0] i;
// always @(posedge clk) begin
// for (i = 0; i < 32; i++) begin
// $display("%d: %h",i, registers[i[4:0]]);
// end
// end
// integer i;
assign write_data = in_data;
assign write_register = in_rd;
// always @(*) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
always @(posedge clk) begin
if(write_enable && !in_wspawn) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_wspawn && in_to_wspawn) begin
// $display("WSPAWN IN MASTER SLAVE");
registers <= in_wspawn_regs;
end
end
// always @(posedge clk) begin
// for (i = 0; i < 32; i = i + 1)
// $display("(%d): %x", i, registers[i]);
// end
always @(negedge clk) begin
out_src1_data <= registers[in_src1];
out_src2_data <= registers[in_src2];
end
endmodule

15
rtl/VX_register_file_slave.v
View File

@@ -6,6 +6,7 @@
module VX_register_file_slave (
input wire clk,
input wire in_warp,
input wire in_wb_warp,
input wire in_valid,
input wire in_write_register,
input wire[4:0] in_rd,
@@ -37,17 +38,23 @@ module VX_register_file_slave (
// integer i;
// always @(*) begin
// if (in_warp) begin
// $display("TID: %d: %h",10,registers[10]);
// $display("WID: %d: %h",11,registers[11]);
// end
// end
assign write_data = in_data;
assign write_register = in_rd;
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid;
assign write_enable = (in_write_register && (in_rd != 5'h0)) && in_valid && in_wb_warp;
always @(posedge clk) begin
if(write_enable && !in_clone && in_warp) begin
if(write_enable && !in_clone) begin
// $display("RF: Writing %h to %d",write_data, write_register);
registers[write_register] <= write_data;
end else if (in_clone && in_to_clone) begin
// $display("CLONING IN SLAVE");
end else if (in_clone && in_to_clone && in_warp) begin
registers <= in_regs;
end
end

8
rtl/VX_warp.v
View File

@@ -11,7 +11,8 @@ module VX_warp (
input wire[31:0] in_jal_dest,
input wire in_branch_dir,
input wire[31:0] in_branch_dest,
input wire in_wspawn,
input wire[31:0] in_wspawn_pc,
output wire[31:0] out_PC,
output wire out_valid[`NT_M1:0]
@@ -62,7 +63,10 @@ module VX_warp (
always @(posedge clk or posedge reset) begin
if (reset) begin
real_PC <= 0;
end else if (stall == 1'b0) begin
end else if (in_wspawn == 1'b1) begin
// $display("Inside warp ***** Spawn @ %H",in_wspawn_pc);
real_PC <= in_wspawn_pc;
end else if (!stall) begin
real_PC <= use_PC + 32'h4;
end else begin
real_PC <= use_PC;

30
rtl/Vortex.v
View File

@@ -13,7 +13,8 @@ module Vortex(
output wire[2:0] out_cache_driver_in_mem_read,
output wire[2:0] out_cache_driver_in_mem_write,
output wire out_cache_driver_in_valid[`NT_M1:0],
output wire[31:0] out_cache_driver_in_data[`NT_M1:0]
output wire[31:0] out_cache_driver_in_data[`NT_M1:0],
output wire out_ebreak
);
// wire[31:0] in_cache_driver_out_data[`NT_M1:0];
@@ -25,11 +26,12 @@ module Vortex(
assign curr_PC = fetch_curr_PC;
// From fetch
wire[31:0] fetch_instruction;
wire fetch_delay;
wire[31:0] fetch_curr_PC;
wire fetch_valid[`NT_M1:0];
wire[31:0] fetch_instruction;
wire fetch_delay;
wire[31:0] fetch_curr_PC;
wire fetch_valid[`NT_M1:0];
wire[`NW_M1:0] fetch_warp_num;
wire fetch_ebreak;
// From f_d_register
wire[31:0] f_d_instruction;
@@ -62,7 +64,10 @@ wire decode_valid[`NT_M1:0];
wire decode_clone_stall;
wire decode_change_mask;
wire decode_thread_mask[`NT_M1:0];
wire[`NW_M1:0] decode_warp_num;
wire[`NW_M1:0] decode_warp_num;
wire decode_wspawn;
wire[31:0] decode_wspawn_pc;
wire decode_ebreak;
// From d_e_register
wire[11:0] d_e_csr_address;
@@ -193,7 +198,7 @@ wire debug;
assign debug = 1'b0;
assign interrupt = 1'b0;
assign total_freeze = fetch_delay || memory_delay;
assign out_ebreak = fetch_ebreak;
VX_fetch vx_fetch(
.clk (clk),
@@ -214,12 +219,16 @@ VX_fetch vx_fetch(
.in_change_mask (decode_change_mask),
.in_decode_warp_num (decode_warp_num),
.in_memory_warp_num (memory_warp_num),
.in_wspawn (decode_wspawn),
.in_wspawn_pc (decode_wspawn_pc),
.in_ebreak (decode_ebreak),
.out_instruction (fetch_instruction),
.out_delay (fetch_delay),
.out_curr_PC (fetch_curr_PC),
.out_warp_num (fetch_warp_num),
.out_valid (fetch_valid)
.out_valid (fetch_valid),
.out_ebreak (fetch_ebreak)
);
@@ -280,7 +289,10 @@ VX_decode vx_decode(
.out_clone_stall (decode_clone_stall),
.out_change_mask (decode_change_mask),
.out_thread_mask (decode_thread_mask),
.out_warp_num (decode_warp_num)
.out_warp_num (decode_warp_num),
.out_wspawn (decode_wspawn),
.out_wspawn_pc (decode_wspawn_pc),
.out_ebreak (decode_ebreak)
);

BIN
rtl/obj_dir/VVortex
View File

Binary file not shown.

4435
rtl/obj_dir/VVortex.cpp
View File

File diff suppressed because it is too large Load Diff

107
rtl/obj_dir/VVortex.h
View File

@@ -25,6 +25,7 @@ VL_MODULE(VVortex) {
VL_IN8(reset,0,0);
VL_OUT8(out_cache_driver_in_mem_read,2,0);
VL_OUT8(out_cache_driver_in_mem_write,2,0);
VL_OUT8(out_ebreak,0,0);
VL_IN(fe_instruction,31,0);
VL_OUT(curr_PC,31,0);
VL_IN(in_cache_driver_out_data[2],31,0);
@@ -41,23 +42,35 @@ VL_MODULE(VVortex) {
VL_SIG8(Vortex__DOT__decode_branch_type,2,0);
VL_SIG8(Vortex__DOT__decode_jal,0,0);
VL_SIG8(Vortex__DOT__decode_clone_stall,0,0);
VL_SIG8(Vortex__DOT__decode_change_mask,0,0);
VL_SIG8(Vortex__DOT__execute_branch_stall,0,0);
VL_SIG8(Vortex__DOT__memory_branch_dir,0,0);
VL_SIG8(Vortex__DOT__forwarding_fwd_stall,0,0);
VL_SIG8(Vortex__DOT__forwarding_src1_fwd,0,0);
VL_SIG8(Vortex__DOT__forwarding_src2_fwd,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_state,1,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__add_warp,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__remove_warp,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_stall,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_change_mask,0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_stall,0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__warp_num,1,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_itype,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_csr,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_clone,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jalrs,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_jmprt,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_wspawn,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jal_sys_jal,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__mul_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__is_ebreak,0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__temp_final_alu,4,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__wspawn_state_stall,5,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__rd,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__alu_op,4,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__wb,1,0);
@@ -89,20 +102,24 @@ VL_MODULE(VVortex) {
VL_SIG16(Vortex__DOT__decode_csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_decode__DOT__alu_tempp,11,0);
VL_SIG16(Vortex__DOT__vx_d_e_reg__DOT__csr_address,11,0);
};
struct {
VL_SIG16(Vortex__DOT__vx_e_m_reg__DOT__csr_address,11,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__decode_csr_address,11,0);
VL_SIG(Vortex__DOT__decode_itype_immed,31,0);
VL_SIG(Vortex__DOT__decode_jal_offset,31,0);
VL_SIG(Vortex__DOT__memory_branch_dest,31,0);
VL_SIG(Vortex__DOT__csr_decode_csr_data,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__out_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__real_PC,31,0);
VL_SIG(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__temp_PC,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0);
VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0);
};
struct {
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0);
@@ -142,16 +159,30 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__writeback_write_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__forwarding_src2_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_zero_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__warp_one_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_zero__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT__VX_Warp_one__DOT__valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_f_d_reg__DOT__valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__w0_t0_registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__zero_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__zero_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__one_a_reg_data[2],31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_decode__DOT__one_b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jalrs_thread_mask[2],0,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT__jmprt_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__clone_regsiters[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__clone_regsiters[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd1_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__rd2_register[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__clone_regsiters[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__vx_register_file_master__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__DOT__registers[32],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__b_reg_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_d_e_reg__DOT__valid[2],0,0);
@@ -167,8 +198,6 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT__vx_writeback__DOT__out_pc_data[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_execute_PC_next[2],31,0);
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_memory_PC_next[2],31,0);
};
struct {
VL_SIG(Vortex__DOT__vx_forwarding__DOT__use_writeback_PC_next[2],31,0);
VL_SIG16(Vortex__DOT__vx_csr_handler__DOT__csr[4096],11,0);
};
@@ -179,13 +208,16 @@ VL_MODULE(VVortex) {
struct {
// Begin mtask footprint all:
VL_SIG8(__Vtableidx1,2,0);
VL_SIG8(__Vdly__Vortex__DOT__vx_fetch__DOT__warp_num,1,0);
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src2_data,31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__out_src1_data,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__0__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG(Vortex__DOT__vx_execute__DOT____Vcellout__genblk1__BRA__1__KET____DOT__vx_alu__out_alu_result,31,0);
VL_SIG8(Vortex__DOT____Vcellout__vx_fetch__out_valid[2],0,0);
@@ -239,24 +271,37 @@ VL_MODULE(VVortex) {
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_mem_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_writeback__in_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src2_fwd_data[2],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellout__vx_forwarding__out_src1_fwd_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_writeback_alu_result[2],31,0);
};
struct {
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_mem_data[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_memory_alu_result[2],31,0);
VL_SIG(Vortex__DOT____Vcellinp__vx_forwarding__in_execute_alu_result[2],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp__out_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp__in_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_write_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context__in_valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_zero__out_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_zero__in_thread_mask[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellout__VX_Warp_one__out_valid[2],0,0);
VL_SIG8(Vortex__DOT__vx_fetch__DOT____Vcellinp__VX_Warp_one__in_thread_mask[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__w0_t0_registers[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_zero__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_write_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_zero__in_valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_b_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellout__VX_Context_one__out_a_reg_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_wspawn_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_write_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src2_fwd_data[2],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_src1_fwd_data[2],31,0);
VL_SIG8(Vortex__DOT__vx_decode__DOT____Vcellinp__VX_Context_one__in_valid[2],0,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_zero__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellout__vx_register_file_master__out_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__vx_register_file_master__in_wspawn_regs[32],31,0);
VL_SIG(Vortex__DOT__vx_decode__DOT__VX_Context_one__DOT____Vcellinp__gen_code_label__BRA__1__KET____DOT__vx_register_file_slave__in_regs[32],31,0);
};
static VL_ST_SIG8(__Vtable1_Vortex__DOT__vx_decode__DOT__mul_alu[8],4,0);

BIN
rtl/obj_dir/VVortex__ALL.a
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BIN
rtl/obj_dir/VVortex__ALLcls.o
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2
rtl/obj_dir/VVortex__ver.d
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@@ -1 +1 @@
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v
obj_dir/VVortex.cpp obj_dir/VVortex.h obj_dir/VVortex.mk obj_dir/VVortex__Syms.cpp obj_dir/VVortex__Syms.h obj_dir/VVortex__ver.d obj_dir/VVortex_classes.mk : /usr/local/Cellar/verilator/4.010/bin/verilator_bin /usr/local/Cellar/verilator/4.010/bin/verilator_bin VX_alu.v VX_context.v VX_context_slave.v VX_csr_handler.v VX_d_e_reg.v VX_decode.v VX_define.v VX_e_m_reg.v VX_execute.v VX_f_d_reg.v VX_fetch.v VX_forwarding.v VX_m_w_reg.v VX_memory.v VX_register_file.v VX_register_file_master_slave.v VX_register_file_slave.v VX_warp.v VX_writeback.v Vortex.v

36
rtl/obj_dir/VVortex__verFiles.dat
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@@ -2,28 +2,30 @@
C "-Wall -cc Vortex.v --exe test_bench.cpp"
S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin"
S 2785 12889457986 1554064009 0 1554064009 0 "VX_alu.v"
S 3288 12890338917 1557354788 0 1557354788 0 "VX_context.v"
S 3486 12890338917 1557473618 0 1557473618 0 "VX_context.v"
S 4928 12890355578 1557474515 0 1557474515 0 "VX_context_slave.v"
S 1495 12889457987 1554023089 0 1554023089 0 "VX_csr_handler.v"
S 5512 12889457988 1557345046 0 1557345046 0 "VX_d_e_reg.v"
S 12085 12890307904 1557354665 0 1557354665 0 "VX_decode.v"
S 14563 12890307904 1557474495 0 1557474495 0 "VX_decode.v"
S 1574 12890307906 1557343909 0 1557343909 0 "VX_define.v"
S 4267 12889457992 1557345117 0 1557345117 0 "VX_e_m_reg.v"
S 3405 12889457993 1557348460 0 1557348460 0 "VX_execute.v"
S 3692 12889457993 1557447660 0 1557447660 0 "VX_execute.v"
S 1751 12889457994 1557344924 0 1557344924 0 "VX_f_d_reg.v"
S 2362 12890309989 1557358323 0 1557358323 0 "VX_fetch.v"
S 4619 12890309989 1557474372 0 1557474372 0 "VX_fetch.v"
S 6293 12889457996 1557348346 0 1557348346 0 "VX_forwarding.v"
S 1866 12889457997 1557348551 0 1557348551 0 "VX_m_w_reg.v"
S 3847 12890309990 1557348518 0 1557348518 0 "VX_memory.v"
S 1118 12889457999 1557354753 0 1557354753 0 "VX_register_file.v"
S 1428 12889458000 1557354772 0 1557354772 0 "VX_register_file_slave.v"
S 1499 12890308905 1557267602 0 1557267602 0 "VX_warp.v"
S 4352 12890309990 1557474440 0 1557474440 0 "VX_memory.v"
S 1249 12889457999 1557474005 0 1557474005 0 "VX_register_file.v"
S 1655 12890356143 1557474338 0 1557474338 0 "VX_register_file_master_slave.v"
S 1599 12889458000 1557474345 0 1557474345 0 "VX_register_file_slave.v"
S 1686 12890308905 1557474462 0 1557474462 0 "VX_warp.v"
S 1568 12890307909 1557348531 0 1557348531 0 "VX_writeback.v"
S 18244 12890307910 1557357447 0 1557357447 0 "Vortex.v"
T 277561 12890339974 1557358338 0 1557358338 0 "obj_dir/VVortex.cpp"
T 16771 12890339973 1557358338 0 1557358338 0 "obj_dir/VVortex.h"
T 1800 12890339976 1557358338 0 1557358338 0 "obj_dir/VVortex.mk"
T 530 12890339972 1557358338 0 1557358338 0 "obj_dir/VVortex__Syms.cpp"
T 711 12890339971 1557358338 0 1557358338 0 "obj_dir/VVortex__Syms.h"
T 512 12890339977 1557358338 0 1557358338 0 "obj_dir/VVortex__ver.d"
T 0 0 1557358338 0 1557358338 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12890339975 1557358338 0 1557358338 0 "obj_dir/VVortex_classes.mk"
S 18714 12890307910 1557368874 0 1557368874 0 "Vortex.v"
T 451065 12890356589 1557474518 0 1557474518 0 "obj_dir/VVortex.cpp"
T 20559 12890356588 1557474518 0 1557474518 0 "obj_dir/VVortex.h"
T 1800 12890356591 1557474518 0 1557474518 0 "obj_dir/VVortex.mk"
T 530 12890356587 1557474518 0 1557474518 0 "obj_dir/VVortex__Syms.cpp"
T 711 12890356586 1557474518 0 1557474518 0 "obj_dir/VVortex__Syms.h"
T 563 12890356592 1557474518 0 1557474518 0 "obj_dir/VVortex__ver.d"
T 0 0 1557474518 0 1557474518 0 "obj_dir/VVortex__verFiles.dat"
T 1159 12890356590 1557474518 0 1557474518 0 "obj_dir/VVortex_classes.mk"

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8
rtl/results.txt
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@@ -1,7 +1,7 @@
# Dynamic Instructions: 122612
# of total cycles: 122624
# Dynamic Instructions: 222955
# of total cycles: 222962
# of forwarding stalls: 0
# of branch stalls: 0
# CPI: 1.0001
# CPI: 1.00003
# time to simulate: 6.95312e-310 milliseconds
# GRADE: Failed on test: 0
# GRADE: Failed on test: 4294967295

11
rtl/test_bench.h
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@@ -326,11 +326,12 @@ bool Vortex::simulate(std::string file_to_simulate)
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
// unsigned cycles;
while (this->stop && (!(stop && (counter > 5))))
counter = 0;
while (this->stop && ((counter < 5)))
{
// std::cout << "************* Cycle: " << cycle << "\n";
@@ -347,10 +348,12 @@ bool Vortex::simulate(std::string file_to_simulate)
vortex->eval();
stop = istop && dstop;
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop)
if (stop || cont)
{
cont = true;
counter++;
} else
{