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minor update

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This commit is contained in:
Blaise Tine
2020-10-25 18:29:25 -07:00
parent 43ae82e788
commit 48897d9778
2 changed files with 21 additions and 25 deletions
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9
driver/opae/vlsim/opae_sim.cpp
View File

@@ -206,11 +206,10 @@ void opae_sim::sRxPort_bus() {
vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1; vortex_afu_->vcp2af_sRxPort_c0_rspValid = 1;
memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_rd_it->block.data(), CACHE_BLOCK_SIZE); memcpy(vortex_afu_->vcp2af_sRxPort_c0_data, cci_rd_it->block.data(), CACHE_BLOCK_SIZE);
vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata; vortex_afu_->vcp2af_sRxPort_c0_hdr_mdata = cci_rd_it->mdata;
printf("*** [vlsim] read-rsp: addr=%ld, mdata=%d, data=", cci_rd_it->addr, cci_rd_it->mdata); /*printf("*** [vlsim] read-rsp: addr=%ld, mdata=%d, data=", cci_rd_it->addr, cci_rd_it->mdata);
for (int i = 0; i < CACHE_BLOCK_SIZE; ++i) { for (int i = 0; i < CACHE_BLOCK_SIZE; ++i)
printf("%02x", cci_rd_it->block[CACHE_BLOCK_SIZE-1-i]); printf("%02x", cci_rd_it->block[CACHE_BLOCK_SIZE-1-i]);
} printf("\n");*/
printf("\n");
fflush(stdout); fflush(stdout);
cci_reads_.erase(cci_rd_it); cci_reads_.erase(cci_rd_it);
} }
@@ -226,7 +225,7 @@ void opae_sim::sTxPort_bus() {
cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata; cci_req.mdata = vortex_afu_->af2cp_sTxPort_c0_hdr_mdata;
auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE); auto host_ptr = (uint64_t*)(vortex_afu_->af2cp_sTxPort_c0_hdr_address * CACHE_BLOCK_SIZE);
memcpy(cci_req.block.data(), host_ptr, CACHE_BLOCK_SIZE); memcpy(cci_req.block.data(), host_ptr, CACHE_BLOCK_SIZE);
printf("*** [vlsim] read-req: addr=%ld, mdata=%d\n", vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata); //printf("*** [vlsim] read-req: addr=%ld, mdata=%d\n", vortex_afu_->af2cp_sTxPort_c0_hdr_address, cci_req.mdata);
fflush(stdout); fflush(stdout);
cci_reads_.emplace_back(cci_req); cci_reads_.emplace_back(cci_req);
} }

33
hw/opae/vortex_afu.sv
View File

@@ -746,7 +746,6 @@ always @(posedge clk) begin
cci_rd_req_ctr <= cci_rd_req_ctr_next; cci_rd_req_ctr <= cci_rd_req_ctr_next;
if (cci_rd_req_tag == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin if (cci_rd_req_tag == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin
cci_rd_req_wait <= 1; // end current request batch cci_rd_req_wait <= 1; // end current request batch
$display("*** %t: CCI Rd Rsp: STOP", $time);
end end
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); $display("%t: CCI Rd Req: addr=%0h, tag=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, cci_rd_req_tag, (cmd_data_size - cci_rd_req_ctr_next), cci_pending_reads_next);
@@ -757,7 +756,6 @@ always @(posedge clk) begin
cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_RQ_TAGW'(1); cci_rd_rsp_ctr <= cci_rd_rsp_ctr + CCI_RD_RQ_TAGW'(1);
if (cci_rd_rsp_ctr == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin if (cci_rd_rsp_ctr == CCI_RD_RQ_TAGW'(CCI_RD_WINDOW_SIZE-1)) begin
cci_rd_req_wait <= 0; // restart new request batch cci_rd_req_wait <= 0; // restart new request batch
$display("*** %t: CCI Rd Rsp: START", $time);
end end
`ifdef DBG_PRINT_OPAE `ifdef DBG_PRINT_OPAE
$display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr); $display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr);
@@ -789,26 +787,25 @@ VX_generic_queue #(
`UNUSED_PIN (size) `UNUSED_PIN (size)
); );
`DEBUG_BEGIN `ifdef VERILATOR
reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask; `DEBUG_BLOCK(
always @(posedge clk) begin reg [CCI_RD_WINDOW_SIZE-1:0] dbg_cci_rd_rsp_mask;
if (reset) begin always @(posedge clk) begin
dbg_cci_rd_rsp_mask <= 0; if (reset) begin
end else begin dbg_cci_rd_rsp_mask <= 0;
if (cci_rd_rsp_fire) begin end else begin
if (cci_rd_rsp_ctr == 0) begin if (cci_rd_rsp_fire) begin
dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag); if (cci_rd_rsp_ctr == 0) begin
end else begin dbg_cci_rd_rsp_mask <= (CCI_RD_WINDOW_SIZE'(1) << cci_rd_rsp_tag);
if (dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] != 0) begin end else begin
$display("*** %t: Assert: CCI Rd Rsp: idx=%0d, ctr=%0d, mask=%0h, meta=%0h, data=%0h", $time, cci_rd_rsp_tag, cci_rd_rsp_ctr, dbg_cci_rd_rsp_mask, cp2af_sRxPort.c0.hdr.mdata, cp2af_sRxPort.c0.data); assert(!dbg_cci_rd_rsp_mask[cci_rd_rsp_tag]);
assert(0); dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1;
end end
dbg_cci_rd_rsp_mask[cci_rd_rsp_tag] <= 1;
end end
end end
end end
end )
`DEBUG_END `endif
// CCI-P Write Request ////////////////////////////////////////////////////////// // CCI-P Write Request //////////////////////////////////////////////////////////