reset posedge

2019-10-21 11:34:12 -04:00
parent fd876144f5
commit 4bfdbb5188
1 changed files with 4 additions and 3 deletions
--- a/rtl/VX_generic_register.v
+++ b/rtl/VX_generic_register.v
@@ -16,11 +16,12 @@ module VX_generic_register

 	reg[N-1:0] value;

-	wire do_rest = reset || flush;


-	always @(posedge clk) begin
-		if (do_rest) begin
+	always @(posedge clk or posedge reset) begin
+		if (reset) begin
+			value <= 0;
+		end else if (flush) begin
 			value <= 0;
 		end else if (~stall) begin
 			value <= in;