Updated TODO

2019-03-22 04:21:21 -04:00
parent 6c64fa35f8
commit 781c11c93f
13 changed files with 2 additions and 40 deletions
--- a/.gitignore
+++ b/.gitignore
@@ -1,39 +0,0 @@
 *.o
 src/harptool
 src/lex.yy.cc
 src/libharplib.a
 src/libharplib.so
 *.bin
 src/test/2thread.4b.d
 src/test/2thread.4b.out
 src/test/2thread.d
 src/test/2thread.out
 src/test/bubble.4b.d
 src/test/bubble.4b.out
 src/test/bubble.d
 src/test/bubble.out
 src/test/diverge.d
 src/test/diverge.out
 src/test/dotprod.4b.d
 src/test/dotprod.4b.out
 src/test/dotprod.d
 src/test/dotprod.out
 src/test/lfsr.4b.out
 src/test/lfsr.d
 src/test/lfsr.out
 src/test/matmul-mt.d
 src/test/matmul-mt.out
 src/test/matmul.4b.d
 src/test/matmul.4b.out
 src/test/matmul.d
 src/test/matmul.out
 src/test/sieve.4b.d
 src/test/sieve.4b.out
 src/test/sieve.d
 src/test/sieve.out
 src/test/simple.4b.d
 src/test/simple.4b.out
 src/test/simple.d
 src/test/simple.out
 util/bin2mif
--- a/3
+++ b/3
@@ -2,4 +2,5 @@
 * csri bug?
-* Start on the Verilog Pipeline (Research loading into mem)
+* Add hardware threads to rtl
 * Add hardware warps to rtl
--- a/emulator/args.o
+++ b/emulator/args.o
--- a/emulator/core.o
+++ b/emulator/core.o
--- a/emulator/enc.o
+++ b/emulator/enc.o
--- a/emulator/harptool.o
+++ b/emulator/harptool.o
--- a/emulator/instruction.o
+++ b/emulator/instruction.o
--- a/emulator/mem.o
+++ b/emulator/mem.o
--- a/emulator/util.o
+++ b/emulator/util.o
--- a/rtl/obj_dir/VVortex__ALLcls.o
+++ b/rtl/obj_dir/VVortex__ALLcls.o
--- a/rtl/obj_dir/VVortex__ALLsup.o
+++ b/rtl/obj_dir/VVortex__ALLsup.o
--- a/rtl/obj_dir/test_bench.o
+++ b/rtl/obj_dir/test_bench.o
--- a/rtl/obj_dir/verilated.o
+++ b/rtl/obj_dir/verilated.o