Add bare mmio kernel

tests/kernel/gemmini_mmio/Makefile

@@ -0,0 +1,52 @@
+XLEN ?= 32
+
+ifeq ($(XLEN),64)
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv64-gnu-toolchain
+CFLAGS += -march=rv64imafd -mabi=lp64d
+else
+RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
+CFLAGS += -march=rv32imaf -mabi=ilp32f
+endif
+
+RISCV_PREFIX ?= riscv$(XLEN)-unknown-elf
+
+VORTEX_KN_PATH ?= $(realpath ../../../kernel)
+
+CC = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc
+AR = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-gcc-ar
+DP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objdump
+CP = $(RISCV_TOOLCHAIN_PATH)/bin/$(RISCV_PREFIX)-objcopy
+
+SIM_DIR = ../../../sim
+
+CFLAGS += -O3 -v -mcmodel=medany -fno-exceptions -nostartfiles -fdata-sections -ffunction-sections
+CFLAGS += -I$(VORTEX_KN_PATH)/include -I$(VORTEX_KN_PATH)/../hw
+
+LDFLAGS += -lm -Wl,-Bstatic,--gc-sections,-T,$(VORTEX_KN_PATH)/linker/vx_link$(XLEN).ld,--defsym=STARTUP_ADDR=0x80000000 $(VORTEX_KN_PATH)/libvortexrt.a
+
+PROJECT = gemmini_mmio
+
+SRCS = main.cpp
+
+all: $(PROJECT).elf $(PROJECT).bin $(PROJECT).dump
+
+$(PROJECT).dump: $(PROJECT).elf
+	$(DP) -D $(PROJECT).elf > $(PROJECT).dump
+
+$(PROJECT).bin: $(PROJECT).elf
+	$(CP) -O binary $(PROJECT).elf $(PROJECT).bin
+
+$(PROJECT).elf: $(SRCS)
+	$(CC) $(CFLAGS) $(SRCS) $(LDFLAGS) -o $(PROJECT).elf
+
+run-rtlsim: $(PROJECT).bin
+	$(SIM_DIR)/rtlsim/rtlsim $(PROJECT).bin
+
+run-simx: $(PROJECT).bin
+	$(SIM_DIR)/simx/simx $(PROJECT).bin
+
+.depend: $(SRCS)
+	$(CC) $(CFLAGS) -MM $^ > .depend;
+
+clean:
+	rm -rf *.elf *.bin *.dump .depend 

tests/kernel/gemmini_mmio/main.cpp

@@ -0,0 +1,35 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <vx_intrinsics.h>
+#include <vx_print.h>
+
+#define ADDR_LEN 32
+#define XCUSTOM_ACC 3
+#define k_MVOUT_SPAD 23
+
+// fence
+#define gemmini_fence() asm volatile("fence")
+
+#define ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) { \
+    /* printf("function %d\n", funct); */ \
+    uint32_t instruction = (0x7B) | (0 << 7) | (3 << 12) | (1 << 15) | (2 << 20) | ((uint32_t) funct << 25); \
+    *((volatile uint64_t*) 0xff002010) = (uint64_t) (rs1); \
+    *((volatile uint64_t*) 0xff002018) = (uint64_t) (rs2); \
+    /* gemmini_fence(); */ \
+    *((volatile uint32_t*) 0xff002000) = instruction; \
+}
+
+#define gemmini_extended_mvout_spad(dst_addr, dst_stride, src_addr, cols, rows) \
+  ROCC_INSTRUCTION_RS1_RS2(XCUSTOM_ACC, ((uint64_t)(dst_stride) << 32) | (uint64_t)(dst_addr), ((uint64_t)(rows) << (ADDR_LEN + 16)) | ((uint64_t)(cols) << ADDR_LEN) | (uint64_t)(src_addr), k_MVOUT_SPAD)
+
+#define gemmini_mvout_spad(dst_addr, src_addr, cols, rows) \
+  gemmini_extended_mvout_spad(dst_addr, 1, src_addr, cols, rows)
+
+int main() {
+  gemmini_mvout_spad(0xff000000, 0xff000100, 4, 4);
+
+  // volatile uint32_t *ptr_cmd = (volatile uint32_t *)0xff100000;
+  // *ptr_cmd = 0xdeadbeef;
+
+  return 0;
+}