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minor update

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This commit is contained in:
Blaise Tine
2021-06-28 08:00:29 -07:00
parent 2d878b25a6
commit 86aabbbf5d
2 changed files with 4 additions and 4 deletions
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6
driver/opae/vlsim/opae_sim.cpp
View File

@@ -307,7 +307,7 @@ void opae_sim::avs_bus() {
memcpy(vortex_afu_->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE); memcpy(vortex_afu_->avs_readdata[b], mem_rd_it->data.data(), MEM_BLOCK_SIZE);
uint32_t addr = mem_rd_it->addr; uint32_t addr = mem_rd_it->addr;
mem_reads_[b].erase(mem_rd_it); mem_reads_[b].erase(mem_rd_it);
/*printf("%0ld: [sim] MEM Rd Rsp: addr=%x, pending={", timestamp, addr * MEM_BLOCK_SIZE); /*printf("%0ld: [sim] MEM Rd Rsp: bank=%d, addr=%x, pending={", timestamp, b, addr * MEM_BLOCK_SIZE);
for (auto& req : mem_reads_[b]) { for (auto& req : mem_reads_[b]) {
if (req.cycles_left != 0) if (req.cycles_left != 0)
printf(" !%0x", req.addr * MEM_BLOCK_SIZE); printf(" !%0x", req.addr * MEM_BLOCK_SIZE);
@@ -340,7 +340,7 @@ void opae_sim::avs_bus() {
ram_[base_addr + i] = data[i]; ram_[base_addr + i] = data[i];
} }
} }
/*printf("%0ld: [sim] MEM Wr Req: addr=%x, data=", timestamp, base_addr); /*printf("%0ld: [sim] MEM Wr Req: bank=%d, addr=%x, data=", timestamp, b, base_addr);
for (int i = 0; i < MEM_BLOCK_SIZE; i++) { for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
printf("%0x", data[(MEM_BLOCK_SIZE-1)-i]); printf("%0x", data[(MEM_BLOCK_SIZE-1)-i]);
} }
@@ -358,7 +358,7 @@ void opae_sim::avs_bus() {
} }
} }
mem_reads_[b].emplace_back(mem_req); mem_reads_[b].emplace_back(mem_req);
/*printf("%0ld: [sim] MEM Rd Req: addr=%x, pending={", timestamp, mem_req.addr * MEM_BLOCK_SIZE); /*printf("%0ld: [sim] MEM Rd Req: bank=%d, addr=%x, pending={", timestamp, b, mem_req.addr * MEM_BLOCK_SIZE);
for (auto& req : mem_reads_[b]) { for (auto& req : mem_reads_[b]) {
if (req.cycles_left != 0) if (req.cycles_left != 0)
printf(" !%0x", req.addr * MEM_BLOCK_SIZE); printf(" !%0x", req.addr * MEM_BLOCK_SIZE);

2
hw/rtl/afu/VX_to_mem.v
View File

@@ -122,7 +122,7 @@ module VX_to_mem #(
end end
end end
assign mem_rsp_tag_in_w = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_in; assign mem_rsp_tag_in_w = (rsp_ctr != 0) ? mem_rsp_tag_in_r : mem_rsp_tag_in;
`RUNTIME_ASSERT((mem_rsp_tag_in_w == mem_rsp_tag_in), ("oops!")) `RUNTIME_ASSERT(!mem_rsp_in_fire || (mem_rsp_tag_in_w == mem_rsp_tag_in), ("out-of-order memory reponse! cur=%d, expected=%d", mem_rsp_tag_in_w, mem_rsp_tag_in))
wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr}; wire [SRC_ADDR_WIDTH+D-1:0] mem_req_addr_in_qual = {mem_req_addr_in, req_ctr};