minor update
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@@ -302,22 +302,32 @@ module VX_lsu_unit #(
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`SCOPE_ASSIGN (dcache_rsp_fire, dcache_rsp_if.tmask & {`NUM_THREADS{dcache_rsp_fire}});
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`SCOPE_ASSIGN (dcache_rsp_data, dcache_rsp_if.data);
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`SCOPE_ASSIGN (dcache_rsp_tag, mbuf_raddr);
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`ifdef DBG_PRINT_CORE_DCACHE
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`IGNORE_WARNINGS_BEGIN
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reg [`LSUQ_SIZE-1:0][`DCORE_TAG_WIDTH:0] pending_reqs;
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`IGNORE_WARNINGS_END
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`ifndef SYNTHESIS
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reg [`LSUQ_SIZE-1:0][(`NW_BITS + 32 + 64 + 1)-1:0] pending_reqs;
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wire [63:0] delay_timeout = 10000 * (1 ** (`L2_ENABLE + `L3_ENABLE));
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always @(posedge clk) begin
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if (reset) begin
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pending_reqs <= '0;
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end else if (mbuf_push) begin
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pending_reqs[mbuf_waddr] <= {dcache_req_if.tag[0], 1'b1};
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end else if (mbuf_pop) begin
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pending_reqs[mbuf_raddr] <= '0;
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end begin
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if (mbuf_push) begin
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pending_reqs[mbuf_waddr] <= {req_wid, req_pc, $time, 1'b1};
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end else if (mbuf_pop) begin
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pending_reqs[mbuf_raddr] <= '0;
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end
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end
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for (integer i = 0; i < `LSUQ_SIZE; ++i) begin
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if (pending_reqs[i][0]) begin
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assert(($time - pending_reqs[i][1 +: 64]) < delay_timeout) else
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$error("%t: *** D$%0d response timeout: wid=%0d, PC=%0h", $time, CORE_ID, pending_reqs[i][1+64+32 +: `NW_BITS], pending_reqs[i][1+64 +: 32]);
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end
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end
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end
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`endif
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`ifdef DBG_PRINT_CORE_DCACHE
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always @(posedge clk) begin
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if (lsu_req_if.valid && fence_wait) begin
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$display("%t: *** D$%0d fence wait", $time, CORE_ID);
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@@ -345,15 +355,6 @@ module VX_lsu_unit #(
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`PRINT_ARRAY1D(dcache_rsp_if.data, `NUM_THREADS);
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$write(", is_dup=%b\n", rsp_is_dup);
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end
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if (mbuf_full) begin
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$write("%t: *** D$%0d queue-full:", $time, CORE_ID);
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for (integer j = 0; j < `LSUQ_SIZE; j++) begin
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if (pending_reqs[j][0]) begin
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$write(" %0d->%0h", j, pending_reqs[j][1 +: `DCORE_TAG_WIDTH]);
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end
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end
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$write("\n");
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end
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end
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`endif
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