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fixed simX multicore support, added shared memory

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This commit is contained in:
Blaise Tine
2021-03-04 20:45:27 -08:00
parent 5e3a949d2d
commit 8a86bddd3e
18 changed files with 824 additions and 717 deletions
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4
driver/simx/Makefile
View File

@@ -12,8 +12,8 @@ CXXFLAGS += -DDUMP_PERF_STATS
#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1
CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1
CXXFLAGS += $(CONFIGS)

78
driver/simx/vortex.cpp
View File

@@ -62,10 +62,19 @@ private:
class vx_device {
public:
vx_device()
: is_done_(false)
: arch_("rv32i", NUM_CORES, NUM_WARPS, NUM_THREADS)
, decoder_(arch_)
, mmu_(PAGE_SIZE, arch_.wsize(), true)
, cores_(arch_.num_cores())
, is_done_(false)
, is_running_(false)
, thread_(__thread_proc__, this) {
mem_allocation_ = ALLOC_BASE_ADDR;
, thread_(__thread_proc__, this)
, ram_((1<<12), (1<<20)) {
mem_allocation_ = ALLOC_BASE_ADDR;
mmu_.attach(ram_, 0, 0xffffffff);
for (int i = 0; i < arch_.num_cores(); ++i) {
cores_[i] = std::make_shared<vortex::Core>(arch_, decoder_, mmu_, i);
}
}
~vx_device() {
@@ -139,33 +148,34 @@ public:
return 0;
}
int get_csr(int core_id, int addr, unsigned *value) {
*value = cores_.at(core_id)->get_csr(addr, 0, 0);
return 0;
}
int set_csr(int core_id, int addr, unsigned value) {
cores_.at(core_id)->set_csr(addr, value);
return 0;
}
private:
void run() {
vortex::ArchDef arch("rv32i", NUM_CORES, NUM_WARPS, NUM_THREADS);
vortex::Decoder decoder(arch);
vortex::MemoryUnit mu(PAGE_SIZE, arch.wsize(), true);
mu.attach(ram_, 0);
std::vector<std::shared_ptr<vortex::Core>> cores(arch.num_cores());
for (int i = 0; i < arch.num_cores(); ++i) {
cores[i] = std::make_shared<vortex::Core>(arch, decoder, mu, i);
}
void run() {
bool running;
int num_cores = cores_.at(0)->arch().num_cores();
do {
running = false;
for (int i = 0; i < arch.num_cores(); ++i) {
if (!cores[i]->running())
for (int i = 0; i < num_cores; ++i) {
if (!cores_[i]->running())
continue;
running = true;
cores[i]->step();
cores_[i]->step();
}
} while (running);
}
void thread_proc() {
std::cout << "Device ready..." << std::endl;
std::cout << "Device ready..." << std::flush << std::endl;
for (;;) {
mutex_.lock();
@@ -177,7 +187,7 @@ private:
break;
if (is_running) {
std::cout << "Device running..." << std::endl;
std::cout << "Device running..." << std::flush << std::endl;
this->run();
@@ -185,17 +195,21 @@ private:
is_running_ = false;
mutex_.unlock();
std::cout << "Device ready..." << std::endl;
std::cout << "Device ready..." << std::flush << std::endl;
}
}
std::cout << "Device shutdown..." << std::endl;
std::cout << "Device shutdown..." << std::flush << std::endl;
}
static void __thread_proc__(vx_device* device) {
device->thread_proc();
}
vortex::ArchDef arch_;
vortex::Decoder decoder_;
vortex::MemoryUnit mmu_;
std::vector<std::shared_ptr<vortex::Core>> cores_;
bool is_done_;
bool is_running_;
size_t mem_allocation_;
@@ -221,6 +235,10 @@ extern int vx_dev_close(vx_device_h hdevice) {
vx_device *device = ((vx_device*)hdevice);
#ifdef DUMP_PERF_STATS
vx_dump_perf(device, stdout);
#endif
delete device;
return 0;
@@ -357,10 +375,20 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) {
return device->wait(timeout);
}
extern int vx_csr_set(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned /*value*/) {
return -1;
extern int vx_csr_set(vx_device_h hdevice, int core_id, int addr, unsigned value) {
if (nullptr == hdevice)
return -1;
vx_device *device = ((vx_device*)hdevice);
return device->set_csr(core_id, addr, value);
}
extern int vx_csr_get(vx_device_h /*hdevice*/, int /*core_id*/, int /*addr*/, unsigned* /*value*/) {
return -1;
extern int vx_csr_get(vx_device_h hdevice, int core_id, int addr, unsigned *value) {
if (nullptr == hdevice)
return -1;
vx_device *device = ((vx_device*)hdevice);
return device->get_csr(core_id, addr, value);
}

2
hw/modelsim/vortex_dpi.cpp
View File

@@ -54,7 +54,7 @@ void load_file(char * filename)
// printf("Inside load_file\n");
fprintf(stderr, "\n\n\n\n**********************\n");
loadHexImpl(filename, &ram);
loadHexImage(filename, &ram);
// printf("Filename: %s\n", filename);
refill = false;
i_refill = false;

2
hw/rtl/VX_warp_sched.v
View File

@@ -33,7 +33,7 @@ module VX_warp_sched #(
reg [31:0] warp_pcs [`NUM_WARPS-1:0];
// barriers
reg [`NUM_WARPS-1:0] barrier_stall_mask[`NUM_BARRIERS-1:0]; // warps waiting on barrier
reg [`NUM_WARPS-1:0] barrier_stall_mask [`NUM_BARRIERS-1:0]; // warps waiting on barrier
wire reached_barrier_limit; // the expected number of warps reached the barrier
// wspawn

6
simX/archdef.h
View File

@@ -19,6 +19,7 @@ public:
vsize_ = 16;
num_regs_ = 32;
num_csrs_ = 4096;
num_barriers_= NUM_BARRIERS;
num_cores_ = num_cores;
num_warps_ = num_warps;
num_threads_ = num_threads;
@@ -40,6 +41,10 @@ public:
return num_csrs_;
}
int num_barriers() const {
return num_barriers_;
}
int num_threads() const {
return num_threads_;
}
@@ -58,6 +63,7 @@ private:
int vsize_;
int num_regs_;
int num_csrs_;
int num_barriers_;
int num_threads_;
int num_warps_;
int num_cores_;

100
simX/core.cpp
View File

@@ -83,8 +83,10 @@ Core::Core(const ArchDef &arch, Decoder &decoder, MemoryUnit &mem, Word id)
, arch_(arch)
, decoder_(decoder)
, mem_(mem)
, shared_mem_(1, SMEM_SIZE)
, steps_(0)
, num_insts_(0) {
, num_insts_(0) {
foundSchedule_ = true;
schedule_w_ = 0;
@@ -106,6 +108,10 @@ Core::Core(const ArchDef &arch, Decoder &decoder, MemoryUnit &mem, Word id)
fRenameTable_.resize(arch.num_warps(), std::vector<bool>(arch.num_regs(), false));
vRenameTable_.resize(arch.num_regs(), false);
csrs_.resize(arch_.num_csrs());
barriers_.resize(arch_.num_barriers(), 0);
stalled_warps_.resize(arch.num_warps(), false);
for (int i = 0; i < arch_.num_warps(); ++i) {
@@ -147,9 +153,9 @@ void Core::warpScheduler() {
for (size_t wid = 0; wid < warps_.size(); ++wid) {
// round robin scheduling
next_warp = (next_warp + 1) % warps_.size();
bool has_active_threads = warps_[next_warp].active();
bool is_active = warps_[next_warp].active();
bool stalled = stalled_warps_[next_warp];
if (has_active_threads && !stalled) {
if (is_active && !stalled) {
foundSchedule_ = true;
break;
}
@@ -367,6 +373,94 @@ void Core::writeback() {
}
}
Word Core::get_csr(Addr addr, int tid, int wid) {
if (addr == CSR_WTID) {
// Warp threadID
return tid;
} else if (addr == CSR_LTID) {
// Core threadID
return tid + (wid * arch_.num_threads());
} else if (addr == CSR_GTID) {
// Processor threadID
return tid + (wid * arch_.num_threads()) +
(arch_.num_threads() * arch_.num_warps() * id_);
} else if (addr == CSR_LWID) {
// Core warpID
return wid;
} else if (addr == CSR_GWID) {
// Processor warpID
return wid + (arch_.num_warps() * id_);
} else if (addr == CSR_GCID) {
// Processor coreID
return id_;
} else if (addr == CSR_NT) {
// Number of threads per warp
return arch_.num_threads();
} else if (addr == CSR_NW) {
// Number of warps per core
return arch_.num_warps();
} else if (addr == CSR_NC) {
// Number of cores
return arch_.num_cores();
} else if (addr == CSR_INSTRET) {
// NumInsts
return num_insts_;
} else if (addr == CSR_INSTRET_H) {
// NumInsts
return (Word)(num_insts_ >> 32);
} else if (addr == CSR_CYCLE) {
// NumCycles
return (Word)steps_;
} else if (addr == CSR_CYCLE_H) {
// NumCycles
return (Word)(steps_ >> 32);
} else {
return csrs_.at(addr);
}
}
void Core::set_csr(Addr addr, Word value) {
csrs_.at(addr) = value;
}
void Core::barrier(int bar_id, int count, int warp_id) {
auto& barrier = barriers_.at(bar_id);
barrier.set(warp_id);
if (barrier.count() < (size_t)count)
return;
for (int i = 0; i < arch_.num_warps(); ++i) {
if (barrier.test(i)) {
warps_.at(i).activate();
}
}
barrier.reset();
}
Word Core::icache_fetch(Addr addr, bool sup) {
return mem_.fetch(addr, sup);
}
Word Core::dcache_read(Addr addr, bool sup) {
#ifdef SM_ENABLE
if ((addr >= (SHARED_MEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 4) <= SHARED_MEM_BASE_ADDR)) {
return shared_mem_.read(addr & (SMEM_SIZE-1));
}
#endif
return mem_.read(addr, sup);
}
void Core::dcache_write(Addr addr, Word data, bool sup, Size size) {
#ifdef SM_ENABLE
if ((addr >= (SHARED_MEM_BASE_ADDR - SMEM_SIZE))
&& ((addr + 4) <= SHARED_MEM_BASE_ADDR)) {
shared_mem_.write(addr & (SMEM_SIZE-1), data);
return;
}
#endif
mem_.write(addr, data, sup, size);
}
void Core::getCacheDelays(trace_inst_t *trace_inst) {
trace_inst->fetch_stall_cycles += 1;
if (trace_inst->is_sw || trace_inst->is_lw) {

46
simX/core.h
View File

@@ -2,6 +2,7 @@
#include <string>
#include <vector>
#include <list>
#include <stack>
#include <unordered_map>
#include <set>
@@ -23,15 +24,6 @@ public:
bool running() const;
void getCacheDelays(trace_inst_t *);
void warpScheduler();
void fetch();
void decode();
void scheduler();
void execute_unit();
void load_store();
void writeback();
void step();
void printStats() const;
@@ -48,10 +40,6 @@ public:
return decoder_;
}
MemoryUnit& mem() {
return mem_;
}
const ArchDef& arch() const {
return arch_;
}
@@ -66,26 +54,52 @@ public:
unsigned long num_steps() const {
return steps_;
}
}
Word get_csr(Addr addr, int tid, int wid);
void set_csr(Addr addr, Word value);
void barrier(int bar_id, int count, int warp_id);
Word icache_fetch(Addr, bool sup);
Word dcache_read(Addr, bool sup);
void dcache_write(Addr, Word, bool sup, Size);
private:
void fetch();
void decode();
void scheduler();
void execute_unit();
void load_store();
void writeback();
void getCacheDelays(trace_inst_t *);
void warpScheduler();
std::vector<std::vector<bool>> iRenameTable_;
std::vector<std::vector<bool>> fRenameTable_;
std::vector<bool> vRenameTable_;
std::vector<bool> stalled_warps_;
bool foundSchedule_;
Word id_;
const ArchDef &arch_;
Decoder &decoder_;
MemoryUnit &mem_;
#ifdef SM_ENABLE
RAM shared_mem_;
#endif
std::vector<Warp> warps_;
std::unordered_map<Word, std::set<Warp *>> barriers_;
std::vector<WarpMask> barriers_;
std::vector<Word> csrs_;
int schedule_w_;
uint64_t steps_;
uint64_t num_insts_;
Word interruptEntry_;
bool foundSchedule_;
trace_inst_t inst_in_fetch_;
trace_inst_t inst_in_decode_;

3
simX/debug.h
View File

@@ -1,6 +1,7 @@
#pragma once
#define USE_DEBUG 3
//#define USE_DEBUG 3
#define DEBUG_HEADER << "DEBUG "
//#define DEBUG_HEADER << "DEBUG " << __FILE__ << ':' << std::dec << __LINE__ << ": "

3
simX/decode.cpp
View File

@@ -121,7 +121,6 @@ std::shared_ptr<Instr> Decoder::decode(
}
}
// std::cout << "op: " << std::hex << op << " what " << sc_instTable[op].iType << "\n";
switch (curInstType) {
case InstType::N_TYPE:
break;
@@ -311,7 +310,7 @@ std::shared_ptr<Instr> Decoder::decode(
}
}
D(2, "Decoded instr 0x" << std::hex << code << " into: " << instr << std::flush);
D(2, "Decoded instr 0x" << std::hex << code << " into: " << *instr << std::flush);
return instr;
}

410
simX/execute.cpp
View File

@@ -159,6 +159,7 @@ uint8_t fpBinIsInf(uint32_t din) {
void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
assert(tmask_.any());
Word nextPC = PC_;
bool updatePC = false;
bool runOnce = false;
@@ -167,20 +168,21 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
Word func6 = instr.getFunc6();
Word func7 = instr.getFunc7();
Opcode opcode = instr.getOpcode();
int rdest = instr.getRDest();
int rsrc0 = instr.getRSrc(0);
int rsrc1 = instr.getRSrc(1);
int rsrc2 = instr.getRSrc(2);
Word immsrc = instr.getImm();
bool vmask = instr.getVmask();
auto opcode = instr.getOpcode();
int rdest = instr.getRDest();
int rsrc0 = instr.getRSrc(0);
int rsrc1 = instr.getRSrc(1);
int rsrc2 = instr.getRSrc(2);
Word immsrc= instr.getImm();
bool vmask = instr.getVmask();
for (std::size_t t = 0; t < tmask_.count(); t++) {
if (runOnce)
int num_threads = core_->arch().num_threads();
for (int t = 0; t < num_threads; t++) {
if (!tmask_.test(t) || runOnce)
continue;
auto &iregs = iRegFile_[t];
auto &fregs = fRegFile_[t];
auto &iregs = iRegFile_.at(t);
auto &fregs = fRegFile_.at(t);
++insts_;
@@ -197,7 +199,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 0:
// MUL
D(3, "MUL: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = ((int)iregs[rsrc0]) * ((int)iregs[rsrc1]);
if (rdest) iregs[rdest] = ((int)iregs[rsrc0]) * ((int)iregs[rsrc1]);
break;
case 1:
// MULH
@@ -213,7 +215,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
}
// cout << "mulh: " << std::dec << first << " * " << second;
uint64_t result = first * second;
iregs[rdest] = (result >> 32) & 0xFFFFFFFF;
if (rdest) iregs[rdest] = (result >> 32) & 0xFFFFFFFF;
// cout << " = " << result << " or " << iregs[rdest] << "\n";
}
break;
@@ -226,7 +228,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
first = first | 0xFFFFFFFF00000000;
}
int64_t second = (int64_t)iregs[rsrc1];
iregs[rdest] = ((first * second) >> 32) & 0xFFFFFFFF;
if (rdest) iregs[rdest] = ((first * second) >> 32) & 0xFFFFFFFF;
}
break;
case 3:
@@ -236,46 +238,46 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
uint64_t first = (uint64_t)iregs[rsrc0];
uint64_t second = (uint64_t)iregs[rsrc1];
// cout << "MULHU\n";
iregs[rdest] = ((first * second) >> 32) & 0xFFFFFFFF;
if (rdest) iregs[rdest] = ((first * second) >> 32) & 0xFFFFFFFF;
}
break;
case 4:
// DIV
D(3, "DIV: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (iregs[rsrc1] == 0) {
iregs[rdest] = -1;
if (rdest) iregs[rdest] = -1;
break;
}
// cout << "dividing: " << std::dec << ((int) iregs[rsrc0]) << " / " << ((int) iregs[rsrc1]);
iregs[rdest] = ((int)iregs[rsrc0]) / ((int)iregs[rsrc1]);
if (rdest) iregs[rdest] = ((int)iregs[rsrc0]) / ((int)iregs[rsrc1]);
// cout << " = " << ((int) iregs[rdest]) << "\n";
break;
case 5:
// DIVU
D(3, "DIVU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (iregs[rsrc1] == 0) {
iregs[rdest] = -1;
if (rdest) iregs[rdest] = -1;
break;
}
iregs[rdest] = ((uint32_t)iregs[rsrc0]) / ((uint32_t)iregs[rsrc1]);
if (rdest) iregs[rdest] = ((uint32_t)iregs[rsrc0]) / ((uint32_t)iregs[rsrc1]);
break;
case 6:
// REM
D(3, "REM: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (iregs[rsrc1] == 0) {
iregs[rdest] = iregs[rsrc0];
if (rdest) iregs[rdest] = iregs[rsrc0];
break;
}
iregs[rdest] = ((int)iregs[rsrc0]) % ((int)iregs[rsrc1]);
if (rdest) iregs[rdest] = ((int)iregs[rsrc0]) % ((int)iregs[rsrc1]);
break;
case 7:
// REMU
D(3, "REMU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (iregs[rsrc1] == 0) {
iregs[rdest] = iregs[rsrc0];
if (rdest) iregs[rdest] = iregs[rsrc0];
break;
}
iregs[rdest] = ((uint32_t)iregs[rsrc0]) % ((uint32_t)iregs[rsrc1]);
if (rdest) iregs[rdest] = ((uint32_t)iregs[rsrc0]) % ((uint32_t)iregs[rsrc1]);
break;
default:
std::cout << "unsupported MUL/DIV instr\n";
@@ -287,52 +289,52 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 0:
if (func7) {
D(3, "SUBI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] - iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] - iregs[rsrc1];
} else {
D(3, "ADDI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] + iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] + iregs[rsrc1];
}
break;
case 1:
D(3, "SLLI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] << iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] << iregs[rsrc1];
break;
case 2:
D(3, "SLTI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (int(iregs[rsrc0]) < int(iregs[rsrc1])) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
break;
case 3:
D(3, "SLTU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
if (Word(iregs[rsrc0]) < Word(iregs[rsrc1])) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
break;
case 4:
D(3, "XORI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] ^ iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] ^ iregs[rsrc1];
break;
case 5:
if (func7) {
D(3, "SRLI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = int(iregs[rsrc0]) >> int(iregs[rsrc1]);
if (rdest) iregs[rdest] = int(iregs[rsrc0]) >> int(iregs[rsrc1]);
} else {
D(3, "SRLU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = Word(iregs[rsrc0]) >> Word(iregs[rsrc1]);
if (rdest) iregs[rdest] = Word(iregs[rsrc0]) >> Word(iregs[rsrc1]);
}
break;
case 6:
D(3, "ORI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] | iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] | iregs[rsrc1];
break;
case 7:
D(3, "AND: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
iregs[rdest] = iregs[rsrc0] & iregs[rsrc1];
if (rdest) iregs[rdest] = iregs[rsrc0] & iregs[rsrc1];
break;
default:
std::cout << "ERROR: UNSUPPORTED R INST\n";
@@ -346,58 +348,58 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 0:
// ADDI
D(3, "ADDI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=" << immsrc);
iregs[rdest] = iregs[rsrc0] + immsrc;
if (rdest) iregs[rdest] = iregs[rsrc0] + immsrc;
break;
case 2:
// SLTI
D(3, "SLTI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=" << immsrc);
if (int(iregs[rsrc0]) < int(immsrc)) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
break;
case 3: {
// SLTIU
D(3, "SLTIU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=" << immsrc);
if (unsigned(iregs[rsrc0]) < unsigned(immsrc)) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
} break;
case 4:
// XORI
D(3, "XORI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = iregs[rsrc0] ^ immsrc;
if (rdest) iregs[rdest] = iregs[rsrc0] ^ immsrc;
break;
case 6:
// ORI
D(3, "ORI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = iregs[rsrc0] | immsrc;
if (rdest) iregs[rdest] = iregs[rsrc0] | immsrc;
break;
case 7:
// ANDI
D(3, "ANDI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = iregs[rsrc0] & immsrc;
if (rdest) iregs[rdest] = iregs[rsrc0] & immsrc;
break;
case 1:
// SLLI
D(3, "SLLI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = iregs[rsrc0] << immsrc;
if (rdest) iregs[rdest] = iregs[rsrc0] << immsrc;
break;
case 5:
if ((func7 == 0)) {
// SRLI
D(3, "SRLI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=" << immsrc);
Word result = Word(iregs[rsrc0]) >> Word(immsrc);
iregs[rdest] = result;
if (rdest) iregs[rdest] = result;
} else {
// SRAI
D(3, "SRAI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=" << immsrc);
Word op1 = iregs[rsrc0];
Word op2 = immsrc;
iregs[rdest] = op1 >> op2;
if (rdest) iregs[rdest] = op1 >> op2;
}
break;
default:
@@ -409,34 +411,34 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
++loads_;
Word memAddr = ((iregs[rsrc0] + immsrc) & 0xFFFFFFFC);
Word shift_by = ((iregs[rsrc0] + immsrc) & 0x00000003) * 8;
Word data_read = core_->mem().read(memAddr, 0);
Word data_read = core_->dcache_read(memAddr, 0);
trace_inst->is_lw = true;
trace_inst->mem_addresses[t] = memAddr;
switch (func3) {
case 0:
// LBI
D(3, "LBI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
if (rdest) iregs[rdest] = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
break;
case 1:
// LWI
D(3, "LHI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
if (rdest) iregs[rdest] = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
break;
case 2:
// LDI
D(3, "LWI: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = int(data_read & 0xFFFFFFFF);
if (rdest) iregs[rdest] = int(data_read & 0xFFFFFFFF);
break;
case 4:
// LBU
D(3, "LBU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = unsigned((data_read >> shift_by) & 0xFF);
if (rdest) iregs[rdest] = unsigned((data_read >> shift_by) & 0xFF);
break;
case 5:
// LWU
D(3, "LHU: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
iregs[rdest] = unsigned((data_read >> shift_by) & 0xFFFF);
if (rdest) iregs[rdest] = unsigned((data_read >> shift_by) & 0xFFFF);
break;
default:
std::cout << "ERROR: UNSUPPORTED L INST\n";
@@ -453,17 +455,17 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 0:
// SB
D(3, "SB: r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1] << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
core_->mem().write(memAddr, iregs[rsrc1] & 0x000000FF, 0, 1);
core_->dcache_write(memAddr, iregs[rsrc1] & 0x000000FF, 0, 1);
break;
case 1:
// SH
D(3, "SH: r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1] << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
core_->mem().write(memAddr, iregs[rsrc1], 0, 2);
core_->dcache_write(memAddr, iregs[rsrc1], 0, 2);
break;
case 2:
// SW
D(3, "SW: r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1] << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
core_->mem().write(memAddr, iregs[rsrc1], 0, 4);
core_->dcache_write(memAddr, iregs[rsrc1], 0, 4);
break;
default:
std::cout << "ERROR: UNSUPPORTED S INST\n";
@@ -532,11 +534,11 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
break;
case LUI_INST:
D(3, "LUI: r" << std::dec << rdest << " <- imm=0x" << std::hex << immsrc);
iregs[rdest] = (immsrc << 12) & 0xfffff000;
if (rdest) iregs[rdest] = (immsrc << 12) & 0xfffff000;
break;
case AUIPC_INST:
D(3, "AUIPC: r" << std::dec << rdest << " <- imm=0x" << std::hex << immsrc);
iregs[rdest] = ((immsrc << 12) & 0xfffff000) + (PC_ - 4);
if (rdest) iregs[rdest] = ((immsrc << 12) & 0xfffff000) + (PC_ - 4);
break;
case JAL_INST:
D(3, "JAL: r" << std::dec << rdest << " <- imm=0x" << std::hex << immsrc);
@@ -545,9 +547,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
nextPC = (PC_ - 4) + immsrc;
//std::cout << "JAL... SETTING PC: " << nextPC << "\n";
}
if (rdest != 0) {
iregs[rdest] = PC_;
}
if (rdest) iregs[rdest] = PC_;
updatePC = true;
break;
case JALR_INST:
@@ -557,109 +557,53 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
nextPC = iregs[rsrc0] + immsrc;
//std::cout << "JALR... SETTING PC: " << nextPC << "\n";
}
if (rdest != 0) {
iregs[rdest] = PC_;
}
if (rdest) iregs[rdest] = PC_;
updatePC = true;
break;
case SYS_INST: {
D(3, "SYS_INST: r" << std::dec << rdest << " <- r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", imm=0x" << std::hex << immsrc);
Word rs1 = iregs[rsrc0];
Word csr_addr = immsrc & 0x00000FFF;
// GPGPU CSR extension
if (csr_addr == CSR_WTID) {
// Warp threadID
iregs[rdest] = t;
} else if (csr_addr == CSR_LTID) {
// Core threadID
iregs[rdest] = t + (id_ * core_->arch().num_threads());
} else if (csr_addr == CSR_GTID) {
// Processor threadID
iregs[rdest] = t + (id_ * core_->arch().num_threads()) +
(core_->arch().num_threads() * core_->arch().num_warps() * core_->id());
} else if (csr_addr == CSR_LWID) {
// Core warpID
iregs[rdest] = id_;
} else if (csr_addr == CSR_GWID) {
// Processor warpID
iregs[rdest] = id_ + (core_->arch().num_warps() * core_->id());
} else if (csr_addr == CSR_GCID) {
// Processor coreID
iregs[rdest] = core_->id();
} else if (csr_addr == CSR_NT) {
// Number of threads per warp
iregs[rdest] = core_->arch().num_threads();
} else if (csr_addr == CSR_NW) {
// Number of warps per core
iregs[rdest] = core_->arch().num_warps();
} else if (csr_addr == CSR_NC) {
// Number of cores
iregs[rdest] = core_->arch().num_cores();
} else if (csr_addr == CSR_INSTRET) {
// NumInsts
iregs[rdest] = (Word)core_->num_insts();
} else if (csr_addr == CSR_INSTRET_H) {
// NumInsts
iregs[rdest] = (Word)(core_->num_insts() >> 32);
} else if (csr_addr == CSR_CYCLE) {
// NumCycles
iregs[rdest] = (Word)core_->num_steps();
} else if (csr_addr == CSR_CYCLE_H) {
// NumCycles
iregs[rdest] = (Word)(core_->num_steps() >> 32);
} else {
switch (func3) {
case 0:
if (csr_addr < 2) {
// ECALL/EBREAK
tmask_.reset();
}
break;
case 1:
// CSRRW
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rs1;
break;
case 2:
// CSRRS
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rs1 | csrs_[csr_addr];
break;
case 3:
// CSRRC
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rs1 & (~csrs_[csr_addr]);
break;
case 5:
// CSRRWI
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rsrc0;
break;
case 6:
// CSRRSI
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rsrc0 | csrs_[csr_addr];
break;
case 7:
// CSRRCI
if (rdest != 0) {
iregs[rdest] = csrs_[csr_addr];
}
csrs_[csr_addr] = rsrc0 & (~csrs_[csr_addr]);
break;
default:
break;
switch (func3) {
case 0:
if (csr_addr < 2) {
// ECALL/EBREAK
tmask_.reset();
active_ = tmask_.any();
}
break;
case 1:
// CSRRW
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rs1);
break;
case 2:
// CSRRS
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rs1 | core_->get_csr(csr_addr, t, id_));
break;
case 3:
// CSRRC
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rs1 & ~core_->get_csr(csr_addr, t, id_));
break;
case 5:
// CSRRWI
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rsrc0);
break;
case 6:
// CSRRSI
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rsrc0 | core_->get_csr(csr_addr, t, id_));
break;
case 7:
// CSRRCI
if (rdest) iregs[rdest] = core_->get_csr(csr_addr, t, id_);
core_->set_csr(csr_addr, rsrc0 & ~core_->get_csr(csr_addr, t, id_));
break;
default:
break;
}
} break;
case FENCE:
@@ -684,6 +628,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
for (int i = 0; i < active_threads; ++i) {
tmask_[i] = true;
}
active_ = tmask_.any();
runOnce = true;
} break;
case 1: {
@@ -726,6 +671,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
for (unsigned i = 0; i < e.tmask.size(); ++i) {
tmask_[i] = !e.tmask[i] && tmask_[i];
}
active_ = tmask_.any();
D(3, "Split: New TM");
DX( for (int i = 0; i < core_->arch().num_threads(); ++i) D(3, tmask_[i] << " "); )
@@ -741,6 +687,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
D(2, "Uni branch at join");
printf("NEW DOMESTACK: \n");
tmask_ = domStack_.top().tmask;
active_ = tmask_.any();
domStack_.pop();
break;
}
@@ -757,6 +704,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
DX( for (int i = 0; i < core_->arch().num_threads(); ++i) D(3, tmask_[i] << " "); )
std::cout << "\n";
tmask_ = domStack_.top().tmask;
active_ = tmask_.any();
D(3, "Join: New TM: ");
DX( for (int i = 0; i < core_->arch().num_threads(); ++i) D(3, tmask_[i] << " "); )
@@ -765,7 +713,10 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
runOnce = true;
} break;
case 4: {
// is_barrier
// BAR
D(3, "BAR: r" << std::dec << rsrc0 << "=0x" << std::hex << iregs[rsrc0] << ", r" << std::dec << rsrc1 << "=0x" << std::hex << iregs[rsrc1]);
active_ = false;
core_->barrier(iregs[rsrc0], iregs[rsrc1], id_);
trace_inst->stall_warp = true;
runOnce = true;
} break;
@@ -1667,7 +1618,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
} else if (s0 >= (2 * VLMAX)) {
vl_ = VLMAX;
}
iregs[rdest] = vl_;
if (rdest) iregs[rdest] = vl_;
} break;
default: {
std::abort();
@@ -1681,7 +1632,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
// rs1 is integer is register!
Word memAddr = ((iregs[rsrc0] + immsrc) & 0xFFFFFFFC); // alignment
D(9,"something weird happen!");
Word data_read = core_->mem().read(memAddr, 0);
Word data_read = core_->dcache_read(memAddr, 0);
D(3, "Memaddr");
DPN(3, ' ' << std::setw(8) << std::hex << memAddr << std::endl);
trace_inst->is_lw = true;
@@ -1698,9 +1649,8 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
}
D(3, "LOAD MEM ADDRESS: " << std::hex << memAddr);
} else {
int VLEN = core_->arch().vsize() * 8;
D(3, "Executing vector load");
D(4, "lmul: " << vtype_.vlmul << " VLEN:" << VLEN << "sew: " << vtype_.vsew);
D(4, "lmul: " << vtype_.vlmul << " VLEN:" << (core_->arch().vsize() * 8) << "sew: " << vtype_.vsew);
D(4, "src: " << rsrc0 << " " << iregs[rsrc0]);
D(4, "dest" << rdest);
D(4, "width" << instr.getVlsWidth());
@@ -1711,7 +1661,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 6: { //load word and unit strided (not checking for unit stride)
for (int i = 0; i < vl_; i++) {
Word memAddr = ((iregs[rsrc0]) & 0xFFFFFFFC) + (i * vtype_.vsew / 8);
Word data_read = core_->mem().read(memAddr, 0);
Word data_read = core_->dcache_read(memAddr, 0);
D(4, "Mem addr: " << std::hex << memAddr << " Data read " << data_read);
int *result_ptr = (int *)(vd.data() + i);
*result_ptr = data_read;
@@ -1748,7 +1698,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
break;
case 2:
// //std::cout << std::hex << "FSW: about to write: " << fregs[rsrc1] << " to " << memAddr << "\n";
core_->mem().write(memAddr, fregs[rsrc1], 0, 4);
core_->dcache_write(memAddr, fregs[rsrc1], 0, 4);
break;
case 3:
std::cout << "ERROR: UNSUPPORTED FS INST\n";
@@ -1780,7 +1730,7 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 6: //store word and unit strided (not checking for unit stride)
{
uint32_t value = *(uint32_t *)(vRegFile_[instr.getVs3()].data() + i);
core_->mem().write(memAddr, value, 0, 4);
core_->dcache_write(memAddr, value, 0, 4);
D(4, "store: " << memAddr << " value:" << value);
} break;
default:
@@ -1802,8 +1752,8 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
D(3, "one or two rsrc is NaN!");
// one of them is not quiet NaN, them set FCSR
if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
if (fpBinIsNan(fregs[rsrc0]) && fpBinIsNan(fregs[rsrc1]))
fregs[rdest] = 0x7fc00000; // canonical(quiet) NaN
@@ -1836,28 +1786,28 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
// fcsr defined in riscv
if (fetestexcept(FE_INEXACT)) {
csrs_[0x003] = csrs_[0x003] | 0x1; // set NX bit
csrs_[0x001] = csrs_[0x001] | 0x1; // set NX bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x1); // set NX bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x1); // set NX bit
}
if (fetestexcept(FE_UNDERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x2; // set UF bit
csrs_[0x001] = csrs_[0x001] | 0x2; // set UF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x2); // set UF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x2); // set UF bit
}
if (fetestexcept(FE_OVERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x4; // set OF bit
csrs_[0x001] = csrs_[0x001] | 0x4; // set OF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x4); // set OF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x4); // set OF bit
}
if (fetestexcept(FE_DIVBYZERO)) {
csrs_[0x003] = csrs_[0x003] | 0x8; // set DZ bit
csrs_[0x001] = csrs_[0x001] | 0x8; // set DZ bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x8); // set DZ bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x8); // set DZ bit
}
if (fetestexcept(FE_INVALID)) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NX bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NX bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NX bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NX bit
}
D(4, "fpOut: " << fpOut);
@@ -1897,8 +1847,8 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1])) { // if one of src is NaN
// one of them is not quiet NaN, them set FCSR
if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
if (fpBinIsNan(fregs[rsrc0]) && fpBinIsNan(fregs[rsrc1]))
fregs[rdest] = 0x7fc00000; // canonical(quiet) NaN
@@ -1982,31 +1932,31 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
// fcsr defined in riscv
if (fetestexcept(FE_INEXACT)) {
csrs_[0x003] = csrs_[0x003] | 0x1; // set NX bit
csrs_[0x001] = csrs_[0x001] | 0x1; // set NX bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x1); // set NX bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x1); // set NX bit
}
if (fetestexcept(FE_UNDERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x2; // set UF bit
csrs_[0x001] = csrs_[0x001] | 0x2; // set UF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x2); // set UF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x2); // set UF bit
}
if (fetestexcept(FE_OVERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x4; // set OF bit
csrs_[0x001] = csrs_[0x001] | 0x4; // set OF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x4); // set OF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x4); // set OF bit
}
if (fetestexcept(FE_DIVBYZERO)) {
csrs_[0x003] = csrs_[0x003] | 0x8; // set DZ bit
csrs_[0x001] = csrs_[0x001] | 0x8; // set DZ bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x8); // set DZ bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x8); // set DZ bit
}
if (fetestexcept(FE_INVALID) || outOfRange) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
iregs[rdest] = result;
if (rdest) iregs[rdest] = result;
} break;
// FMV.X.W FCLASS.S
@@ -2015,31 +1965,33 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
if (func3) {
// Examine the value in fpReg rs1 and write to integer rd
// a 10-bit mask to indicate the class of the fp number
iregs[rdest] = 0; // clear all bits
if (rdest) iregs[rdest] = 0; // clear all bits
bool fsign = fregs[rsrc0] & 0x80000000;
uint32_t expo = (fregs[rsrc0]>>23) & 0x000000FF;
uint32_t fraction = fregs[rsrc0] & 0x007FFFFF;
if ((expo==0) && (fraction==0))
iregs[rdest] = fsign? (1<<3) : (1<<4); // +/- 0
else if ((expo==0) && (fraction!=0))
iregs[rdest] = fsign? (1<<2) : (1<<5); // +/- subnormal
else if ((expo==0xFF) && (fraction==0))
iregs[rdest] = fsign? (1<<0) : (1<<7); // +/- infinity
else if ((expo==0xFF) && (fraction!=0))
if (!fsign && (fraction == 0x00400000))
iregs[rdest] = (1<<9); // quiet NaN
else
iregs[rdest] = (1<<8); // signaling NaN
else
iregs[rdest] = fsign? (1<<1) : (1<<6); // +/- normal
if ((expo==0) && (fraction==0)) {
if (rdest) iregs[rdest] = fsign? (1<<3) : (1<<4); // +/- 0
} else if ((expo==0) && (fraction!=0)) {
if (rdest) iregs[rdest] = fsign? (1<<2) : (1<<5); // +/- subnormal
} else if ((expo==0xFF) && (fraction==0)) {
if (rdest) iregs[rdest] = fsign? (1<<0) : (1<<7); // +/- infinity
} else if ((expo==0xFF) && (fraction!=0)) {
if (!fsign && (fraction == 0x00400000)) {
if (rdest) iregs[rdest] = (1<<9); // quiet NaN
} else {
if (rdest) iregs[rdest] = (1<<8); // signaling NaN
}
} else {
if (rdest) iregs[rdest] = fsign? (1<<1) : (1<<6); // +/- normal
}
} else {
// FMV.X.W
// Move bit values from floating-point register rs1 to integer register rd
// Since we are using integer register to represent floating point register,
// just simply assign here.
iregs[rdest] = fregs[rsrc0];
if (rdest) iregs[rdest] = fregs[rsrc0];
}
} break;
@@ -2052,35 +2004,35 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
// FLE.S or FLT.S
if (func3 == 0 || func3 == 1) {
// If either input is NaN, set NV bit
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
} else { // FEQ.S
// Only set NV bit if it is signaling NaN
if (fpBinIsNan(fregs[rsrc0]) == 2 || fpBinIsNan(fregs[rsrc1]) == 2) {
// If either input is NaN, set NV bit
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
}
// The result is 0 if either operand is NaN
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
} else {
switch(func3) {
case 0: {
// FLE.S
if (intregToFloat(fregs[rsrc0]) <= intregToFloat(fregs[rsrc1])) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
} break;
case 1: {
// FLT.S
if (intregToFloat(fregs[rsrc0]) < intregToFloat(fregs[rsrc1])) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
}
break;
@@ -2088,9 +2040,9 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case 2: {
// FEQ.S
if (intregToFloat(fregs[rsrc0]) == intregToFloat(fregs[rsrc1])) {
iregs[rdest] = 1;
if (rdest) iregs[rdest] = 1;
} else {
iregs[rdest] = 0;
if (rdest) iregs[rdest] = 0;
}
}
break;
@@ -2131,16 +2083,16 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
case FMNMSUB: {
// multiplicands are infinity and zero, them set FCSR
if (fpBinIsZero(fregs[rsrc0])|| fpBinIsZero(fregs[rsrc1])|| fpBinIsInf(fregs[rsrc0]) || fpBinIsInf(fregs[rsrc1])) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
if (fpBinIsNan(fregs[rsrc0]) || fpBinIsNan(fregs[rsrc1]) || fpBinIsNan(fregs[rsrc2])) {
// if one of op is NaN
// if addend is not quiet NaN, them set FCSR
if ((fpBinIsNan(fregs[rsrc0])==2) | (fpBinIsNan(fregs[rsrc1])==2) | (fpBinIsNan(fregs[rsrc1])==2)) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
fregs[rdest] = 0x7fc00000; // canonical(quiet) NaN
} else {
@@ -2170,28 +2122,28 @@ void Warp::execute(Instr &instr, trace_inst_t *trace_inst) {
// fcsr defined in riscv
if (fetestexcept(FE_INEXACT)) {
csrs_[0x003] = csrs_[0x003] | 0x1; // set NX bit
csrs_[0x001] = csrs_[0x001] | 0x1; // set NX bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x1); // set NX bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x1); // set NX bit
}
if (fetestexcept(FE_UNDERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x2; // set UF bit
csrs_[0x001] = csrs_[0x001] | 0x2; // set UF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x2); // set UF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x2); // set UF bit
}
if (fetestexcept(FE_OVERFLOW)) {
csrs_[0x003] = csrs_[0x003] | 0x4; // set OF bit
csrs_[0x001] = csrs_[0x001] | 0x4; // set OF bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x4); // set OF bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x4); // set OF bit
}
if (fetestexcept(FE_DIVBYZERO)) {
csrs_[0x003] = csrs_[0x003] | 0x8; // set DZ bit
csrs_[0x001] = csrs_[0x001] | 0x8; // set DZ bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x8); // set DZ bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x8); // set DZ bit
}
if (fetestexcept(FE_INVALID)) {
csrs_[0x003] = csrs_[0x003] | 0x10; // set NV bit
csrs_[0x001] = csrs_[0x001] | 0x10; // set NV bit
core_->set_csr(0x003, core_->get_csr(0x003, t, id_) | 0x10); // set NV bit
core_->set_csr(0x001, core_->get_csr(0x001, t, id_) | 0x10); // set NV bit
}
fregs[rdest] = floatToBin(fpOut);

5
simX/instr.h
View File

@@ -54,6 +54,7 @@ public:
, nRsrc_(0)
, hasImmSrc_(false)
, hasRDest_(false)
, is_iDest_(false)
, is_FpDest_(false)
, is_VDest_(false)
, is_FpSrc_(0)
@@ -68,7 +69,7 @@ public:
/* Setters used to "craft" the instruction. */
void setOpcode(Opcode opcode) { opcode_ = opcode; }
void setDestReg(int destReg) { hasRDest_ = true; rdest_ = destReg; }
void setDestReg(int destReg) { hasRDest_ = true; is_iDest_ = true; rdest_ = destReg; }
void setSrcReg(int srcReg) { rsrc_[nRsrc_++] = srcReg; }
void setDestFReg(int destReg) { hasRDest_ = true; is_FpDest_ = true; rdest_ = destReg; }
void setSrcFReg(int srcReg) { is_FpSrc_ |= (1 << nRsrc_); rsrc_[nRsrc_++] = srcReg; }
@@ -109,6 +110,7 @@ public:
Word getVsew() const { return vsew_; }
Word getVediv() const { return vediv_; }
bool is_iDest() const { return is_iDest_; }
bool is_FpDest() const { return is_FpDest_; }
bool is_FpSrc(int i) const { return (is_FpSrc_ >> i) & 0x1; }
@@ -125,6 +127,7 @@ private:
int nRsrc_;
bool hasImmSrc_;
bool hasRDest_;
bool is_iDest_;
bool is_FpDest_;
bool is_VDest_;
int is_FpSrc_;

9
simX/main.cpp
View File

@@ -48,11 +48,12 @@ int main(int argc, char **argv) {
ArchDef arch(archString, num_cores, num_warps, num_threads);
Decoder decoder(arch);
MemoryUnit mu(4096, arch.wsize(), true);
MemoryUnit mu(0, arch.wsize(), true);
RAM old_ram;
old_ram.loadHexImpl(imgFileName.c_str());
mu.attach(old_ram, 0);
RAM old_ram((1<<12), (1<<20));
old_ram.loadHexImage(imgFileName.c_str());
mu.attach(old_ram, 0, 0xFFFFFFFF);
struct stat hello;
fstat(0, &hello);

378
simX/mem.cpp
View File

@@ -3,7 +3,9 @@
#include <iomanip>
#include <string>
#include <vector>
#include <algorithm>
#include <stdlib.h>
#include <assert.h>
#include "debug.h"
#include "types.h"
@@ -13,8 +15,8 @@
using namespace vortex;
RamMemDevice::RamMemDevice(const char *filename, Size wordSize)
: wordSize(wordSize), contents() {
RamMemDevice::RamMemDevice(const char *filename, Size wordSize)
: wordSize_(wordSize) {
std::ifstream input(filename);
if (!input) {
@@ -23,15 +25,17 @@ RamMemDevice::RamMemDevice(const char *filename, Size wordSize)
}
do {
contents.push_back(input.get());
contents_.push_back(input.get());
} while (input);
while (contents.size() % wordSize)
contents.push_back(0x00);
while (contents_.size() % wordSize)
contents_.push_back(0x00);
}
RamMemDevice::RamMemDevice(Size size, Size wordSize)
: wordSize(wordSize), contents(size) {}
: wordSize_(wordSize)
, contents_(size)
{}
void RomMemDevice::write(Addr, Word) {
std::cout << "Attempt to write to ROM.\n";
@@ -40,87 +44,81 @@ void RomMemDevice::write(Addr, Word) {
Word RamMemDevice::read(Addr addr) {
D(2, "RAM read, addr=0x" << std::hex << addr);
Word w = readWord(contents, addr, wordSize - addr % wordSize);
Word w = readWord(contents_, addr, wordSize_ - addr % wordSize_);
return w;
}
void RamMemDevice::write(Addr addr, Word w) {
D(2, "RAM write, addr=0x" << std::hex << addr);
writeWord(contents, addr, wordSize - addr % wordSize, w);
writeWord(contents_, addr, wordSize_ - addr % wordSize_, w);
}
MemDevice &MemoryUnit::ADecoder::doLookup(Addr a, Size &bit) {
if (range == 0 || (a & ((1ll << bit) - 1)) >= range) {
ADecoder *p(((a >> bit) & 1) ? oneChild : zeroChild);
if (p) {
bit--;
return p->doLookup(a, bit);
} else {
std::cout << "lookup of 0x" << std::hex << a << " failed.\n";
throw BadAddress();
///////////////////////////////////////////////////////////////////////////////
bool MemoryUnit::ADecoder::lookup(Addr a, Size wordSize, mem_accessor_t* ma) {
Addr e = a + (wordSize - 1);
assert(e >= a);
for (auto iter = entries_.rbegin(), iterE = entries_.rend(); iter != iterE; ++iter) {
if (a >= iter->start && e <= iter->end) {
ma->md = iter->md;
ma->addr = a - iter->start;
return true;
}
} else {
return *md;
}
return false;
}
void MemoryUnit::ADecoder::map(Addr a, MemDevice &m, Size r, Size bit) {
if ((1llu << bit) <= r) {
md = &m;
range = m.size();
} else {
ADecoder *&child(((a >> bit) & 1) ? oneChild : zeroChild);
if (!child)
child = new ADecoder();
child->map(a, m, r, bit - 1);
}
}
Byte *MemoryUnit::ADecoder::getPtr(Addr a, Size sz, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
a &= (2 << bit) - 1;
if (a + sz <= m.size())
return m.base() + a;
return NULL;
void MemoryUnit::ADecoder::map(Addr a, Addr e, MemDevice &m) {
assert(e >= a);
entry_t entry{&m, a, e};
entries_.emplace_back(entry);
}
Word MemoryUnit::ADecoder::read(Addr a, bool /*sup*/, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
a &= (2 << bit) - 1;
return m.read(a);
mem_accessor_t ma;
if (!this->lookup(a, wordSize, &ma)) {
std::cout << "lookup of 0x" << std::hex << a << " failed.\n";
throw BadAddress();
}
return ma.md->read(ma.addr);
}
void MemoryUnit::ADecoder::write(Addr a, Word w, bool /*sup*/, Size wordSize) {
Size bit = wordSize - 1;
MemDevice &m(doLookup(a, bit));
RAM &r = (RAM &)m;
mem_accessor_t ma;
if (!this->lookup(a, wordSize, &ma)) {
std::cout << "lookup of 0x" << std::hex << a << " failed.\n";
throw BadAddress();
}
RAM *ram = (RAM *)ma.md;
if (wordSize == 8) {
r.writeByte(a, &w);
ram->writeByte(ma.addr, &w);
} else if (wordSize == 16) {
r.writeHalf(a, &w);
ram->writeHalf(ma.addr, &w);
} else {
r.writeWord(a, &w);
ram->writeWord(ma.addr, &w);
}
}
Byte *MemoryUnit::getPtr(Addr a, Size s) {
return ad.getPtr(a, s, addrBytes * 8);
///////////////////////////////////////////////////////////////////////////////
MemoryUnit::MemoryUnit(Size pageSize, Size addrBytes, bool disableVm)
: pageSize_(pageSize)
, addrBytes_(addrBytes)
, disableVm_(disableVm) {
if (!disableVm) {
tlb_[0] = TLBEntry(0, 077);
}
}
void MemoryUnit::attach(MemDevice &m, Addr base) {
ad.map(base, m, m.size(), addrBytes * 8 - 1);
void MemoryUnit::attach(MemDevice &m, Addr start, Addr end) {
decoder_.map(start, end, m);
}
MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) {
std::unordered_map<Addr, MemoryUnit::TLBEntry>::iterator i;
if ((i = tlb.find(vAddr / pageSize)) != tlb.end()) {
TLBEntry &t = i->second;
if (t.flags & flagMask)
return t;
auto iter = tlb_.find(vAddr / pageSize_);
if (iter != tlb_.end()) {
if (iter->second.flags & flagMask)
return iter->second;
else {
D(2, "Page fault on addr 0x" << std::hex << vAddr << "(bad flags)");
throw PageFault(vAddr, false);
@@ -133,86 +131,81 @@ MemoryUnit::TLBEntry MemoryUnit::tlbLookup(Addr vAddr, Word flagMask) {
Word MemoryUnit::read(Addr vAddr, bool sup) {
Addr pAddr;
if (disableVm) {
if (disableVm_) {
pAddr = vAddr;
} else {
Word flagMask = sup ? 8 : 1;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn * pageSize + vAddr % pageSize;
TLBEntry t = this->tlbLookup(vAddr, flagMask);
pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
}
// std::cout << "MU::write: About to read: " << std::hex << pAddr << " = " << (ad.read(pAddr, sup, 8*addrBytes)) << " with " << std::dec << (8*addrBytes) << "\n";
return ad.read(pAddr, sup, 8 * addrBytes);
return decoder_.read(pAddr, sup, addrBytes_);
}
Word MemoryUnit::fetch(Addr vAddr, bool sup) {
Addr pAddr;
if (disableVm) {
if (disableVm_) {
pAddr = vAddr;
} else {
Word flagMask = sup ? 32 : 4;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn * pageSize + vAddr % pageSize;
TLBEntry t = this->tlbLookup(vAddr, flagMask);
pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
}
Word instruction = ad.read(pAddr, sup, 8 * addrBytes);
Word instruction = decoder_.read(pAddr, sup, addrBytes_);
return instruction;
}
void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) {
Addr pAddr;
if (disableVm) {
if (disableVm_) {
pAddr = vAddr;
} else {
Word flagMask = sup ? 16 : 2;
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn * pageSize + vAddr % pageSize;
pAddr = t.pfn * pageSize_ + vAddr % pageSize_;
}
// std::cout << "MU::write: About to write: " << std::hex << pAddr << " = " << w << " with " << std::dec << 8*bytes << "\n";
ad.write(pAddr, w, sup, 8 * bytes);
// std::cout << std::hex << "reading same address: " << (this->read(vAddr, sup)) << "\n";
decoder_.write(pAddr, w, sup, bytes);
}
void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) {
D(1, "tlbAdd(0x" << std::hex << virt << ", 0x" << phys << ", 0x" << flags << ')');
tlb[virt / pageSize] = TLBEntry(phys / pageSize, flags);
tlb_[virt / pageSize_] = TLBEntry(phys / pageSize_, flags);
}
void MemoryUnit::tlbRm(Addr va) {
if (tlb.find(va / pageSize) != tlb.end())
tlb.erase(tlb.find(va / pageSize));
if (tlb_.find(va / pageSize_) != tlb_.end())
tlb_.erase(tlb_.find(va / pageSize_));
}
void *vortex::consoleInputThread(void */*arg_vp*/) {
// ConsoleMemDevice *arg = (ConsoleMemDevice *)arg_vp;
// char c;
// while (cin) {
// c = cin.get();
// pthread_mutex_lock(&arg->cBufLock);
// arg->cBuf.push(c);
// pthread_mutex_unlock(&arg->cBufLock);
// }
// cout << "Console input ended. Exiting.\n";
// exit(4);
void *vortex::consoleInputThread(void * /*arg_vp*/) {
//--
return nullptr;
}
///////////////////////////////////////////////////////////////////////////////
DiskControllerMemDevice::DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c)
: wordSize_(wordSize)
, blockSize_(blockSize)
, core_(c)
{}
Word DiskControllerMemDevice::read(Addr a) {
switch (a / 8) {
case 0:
return curDisk;
return curDisk_;
case 1:
return curBlock;
return curBlock_;
case 2:
return disks[curDisk].blocks * blockSize;
return disks_[curDisk_].blocks * blockSize_;
case 3:
return physAddr;
return physAddr_;
case 4:
return command;
return command_;
case 5:
return status;
return status_;
default:
std::cout << "Attempt to read invalid disk controller register.\n";
std::abort();
@@ -222,37 +215,153 @@ Word DiskControllerMemDevice::read(Addr a) {
void DiskControllerMemDevice::write(Addr a, Word w) {
switch (a / 8) {
case 0:
if (w <= disks.size()) {
curDisk = w;
status = OK;
if (w <= disks_.size()) {
curDisk_ = w;
status_ = OK;
} else {
status = INVALID_DISK;
status_ = INVALID_DISK;
}
break;
case 1:
if (w < disks[curDisk].blocks) {
curBlock = w;
if (w < disks_[curDisk_].blocks) {
curBlock_ = w;
} else {
status = INVALID_BLOCK;
status_ = INVALID_BLOCK;
}
break;
case 2:
nBlocks = w >= disks[curDisk].blocks ? disks[curDisk].blocks - 1 : w;
status = OK;
nBlocks_ = w >= disks_[curDisk_].blocks ? disks_[curDisk_].blocks - 1 : w;
status_ = OK;
break;
case 3:
physAddr = w;
status = OK;
physAddr_ = w;
status_ = OK;
break;
case 4:
if (w == 0) {
} else {
}
std::cout << "TODO: Implement disk read and write!\n";
break;
}
}
///////////////////////////////////////////////////////////////////////////////
RAM::RAM(uint32_t num_pages, uint32_t page_size)
: page_bits_(log2ceil(page_size)) {
assert(page_size >= 4);
assert(ispow2(page_size));
mem_.resize(num_pages, NULL);
uint64_t sizel = uint64_t(mem_.size()) << page_bits_;
size_ = (sizel <= 0xFFFFFFFF) ? sizel : 0xffffffff;
}
RAM::~RAM() {
for (auto& page : mem_) {
delete[] page;
}
}
void RAM::clear() {
for (auto& page : mem_) {
delete[] page;
page = NULL;
}
}
Size RAM::size() const {
return size_;
}
uint8_t *RAM::get(uint32_t address) {
uint32_t page_size = 14 << page_bits_;
uint32_t page_index = address >> page_bits_;
uint32_t byte_offset = address & ((1 << page_bits_) - 1);
uint8_t* &page = mem_.at(page_index);
if (page == NULL) {
uint8_t *ptr = new uint8_t[page_size];
for (uint32_t i = 0; i < (page_size / 4); ++i) {
((uint32_t*)ptr)[i] = 0xddccbbaa;
}
page = ptr;
}
return page + byte_offset;
}
void RAM::read(uint32_t address, uint32_t length, uint8_t *data) {
for (unsigned i = 0; i < length; i++) {
data[i] = *this->get(address + i);
}
}
void RAM::write(uint32_t address, uint32_t length, uint8_t *data) {
for (unsigned i = 0; i < length; i++) {
*this->get(address + i) = data[i];
}
}
Byte *RAM::base() {
return (Byte *)this->get(0);
}
void RAM::getBlock(uint32_t address, uint8_t *data) {
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void RAM::getWord(uint32_t address, uint32_t *data) {
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void RAM::writeWord(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++) {
*this->get(address + i) = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void RAM::writeHalf(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++) {
*this->get(address + i) = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void RAM::writeByte(uint32_t address, uint32_t *data) {
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
*this->get(address) = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
void RAM::write(Addr addr, Word w) {
uint32_t word = (uint32_t)w;
writeWord(addr, &word);
}
Word RAM::read(Addr addr) {
uint32_t w;
getWord(addr, &w);
return (Word)w;
}
static uint32_t hti_old(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
@@ -269,58 +378,18 @@ static uint32_t hToI_old(char *c, uint32_t size) {
return value;
}
void RAM::loadHexImpl(std::string path) {
void RAM::loadHexImage(std::string path) {
this->clear();
FILE *fp = fopen(&path[0], "r");
if (fp == 0) {
std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t *)this->get(0))[0] = 0xf1401073;
((uint32_t *)this->get(0))[1] = 0xf1401073;
((uint32_t *)this->get(0))[2] = 0x30101073;
((uint32_t *)this->get(0))[3] = 0x800000b7;
((uint32_t *)this->get(0))[4] = 0x000080e7;
((uint32_t *)this->get(0x80000000))[0] = 0x00000097;
((uint32_t *)this->get(0xb0000000))[0] = 0x01C02023;
((uint32_t *)this->get(0xf00fff10))[0] = 0x12345678;
((uint32_t *)this->get(0x70000000))[0] = 0x00008067;
{
uint32_t init_addr = 0x70000004;
for (int off = 0; off < 1024; off += 4) {
uint32_t new_addr = init_addr + off;
((uint32_t *)this->get(new_addr))[0] = 0x00000000;
}
}
{
uint32_t init_addr = 0x71000000;
for (int off = 0; off < 1024; off += 4) {
uint32_t new_addr = init_addr + off;
((uint32_t *)this->get(new_addr))[0] = 0x00000000;
}
}
{
uint32_t init_addr = 0x72000000;
for (int off = 0; off < 1024; off += 4) {
uint32_t new_addr = init_addr + off;
((uint32_t *)this->get(new_addr))[0] = 0x00000000;
}
}
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char *content = new char[size];
int x = fread(content, 1, size, fp);
if (!x) {
std::cout << "COULD NOT READ FILE\n";
std::abort();
@@ -328,7 +397,7 @@ void RAM::loadHexImpl(std::string path) {
int offset = 0;
char *line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI_old(line + 1, 2);
@@ -338,32 +407,25 @@ void RAM::loadHexImpl(std::string path) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(this->get(add)) = hToI_old(line + 9 + i * 2, 2);
// std::cout << "lhi: Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl;
*this->get(add) = hToI_old(line + 9 + i * 2, 2);
}
break;
case 2:
// cout << offset << std::endl;
offset = hToI_old(line + 9, 4) << 4;
break;
case 4:
// cout << offset << std::endl;
offset = hToI_old(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << std::endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}

468
simX/mem.h
View File

@@ -4,296 +4,228 @@
#include <vector>
#include <queue>
#include <unordered_map>
// #include <pthread.h>
#include "types.h"
namespace vortex {
void *consoleInputThread(void *);
struct BadAddress {};
void *consoleInputThread(void *);
struct BadAddress {};
class MemDevice {
public:
virtual ~MemDevice() {}
virtual Size size() const = 0;
virtual Word read(Addr) = 0;
virtual void write(Addr, Word) = 0;
virtual Byte *base() { return NULL; } /* Null if unavailable. */
class MemDevice {
public:
virtual ~MemDevice() {}
virtual Size size() const = 0;
virtual Word read(Addr) = 0;
virtual void write(Addr, Word) = 0;
virtual Byte *base() {
return NULL;
}
};
///////////////////////////////////////////////////////////////////////////////
class RamMemDevice : public MemDevice {
public:
RamMemDevice(Size size, Size wordSize);
RamMemDevice(const char *filename, Size wordSize);
~RamMemDevice() {}
virtual Word read(Addr);
virtual void write(Addr, Word);
virtual Size size() const {
return contents_.size();
};
class RamMemDevice : public MemDevice {
public:
RamMemDevice(Size size, Size wordSize);
RamMemDevice(const char* filename, Size wordSize);
~RamMemDevice() {}
virtual Byte *base() {
return &contents_[0];
}
virtual Size size() const { return contents.size(); };
virtual Word read(Addr);
virtual void write(Addr, Word);
virtual Byte *base() { return &contents[0]; }
protected:
Size wordSize_;
std::vector<Byte> contents_;
};
protected:
Size wordSize;
std::vector<Byte> contents;
///////////////////////////////////////////////////////////////////////////////
class RomMemDevice : public RamMemDevice {
public:
RomMemDevice(const char *filename, Size wordSize)
: RamMemDevice(filename, wordSize)
{}
RomMemDevice(Size size, Size wordSize)
: RamMemDevice(size, wordSize)
{}
~RomMemDevice();
virtual void write(Addr, Word);
};
///////////////////////////////////////////////////////////////////////////////
class Core;
class DiskControllerMemDevice : public MemDevice {
public:
DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c);
virtual Word read(Addr);
virtual void write(Addr, Word);
virtual Size size() const {
return uint64_t(wordSize_) * 6;
}
void addDisk(Byte *file, Size n) {
disks_.push_back(Disk(file, n));
}
private:
enum Status {
OK = 0,
INVALID_DISK,
INVALID_BLOCK
};
class RomMemDevice : public RamMemDevice {
public:
RomMemDevice(const char* filename, Size wordSize) :
RamMemDevice(filename, wordSize) {}
RomMemDevice(Size size, Size wordSize) :
RamMemDevice(size, wordSize) {}
~RomMemDevice();
virtual void write(Addr, Word);
struct Disk {
Disk(Byte *f, Size n)
: file(f)
, blocks(n)
{}
Byte *file;
Size blocks;
};
class Core;
Word curDisk_;
Word curBlock_;
Word nBlocks_;
Word physAddr_;
Word command_;
Word status_;
Size wordSize_;
Size blockSize_;
Core &core_;
std::vector<Disk> disks_;
};
class DiskControllerMemDevice : public MemDevice {
///////////////////////////////////////////////////////////////////////////////
class MemoryUnit {
public:
MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false);
void attach(MemDevice &m, Addr start, Addr end);
struct PageFault {
PageFault(Addr a, bool nf)
: faultAddr(a)
, notFound(nf)
{}
Addr faultAddr;
bool notFound;
};
Word read(Addr, bool sup);
Word fetch(Addr, bool sup);
void write(Addr, Word, bool sup, Size);
void tlbAdd(Addr virt, Addr phys, Word flags);
void tlbRm(Addr va);
void tlbFlush() {
tlb_.clear();
}
private:
class ADecoder {
public:
DiskControllerMemDevice(Size wordSize, Size blockSize, Core &c) :
wordSize(wordSize), blockSize(blockSize), core(c), disks() {}
ADecoder() {}
void addDisk(Byte *file, Size n) { disks.push_back(Disk(file, n)); }
virtual Size size() const { return wordSize * 6; }
virtual Word read(Addr);
virtual void write(Addr, Word);
Word read(Addr a, bool sup, Size wordSize);
void write(Addr a, Word w, bool sup, Size wordSize);
void map(Addr start, Addr end, MemDevice &md);
private:
Word curDisk, curBlock, nBlocks, physAddr, command, status;
enum Status { OK = 0, INVALID_DISK, INVALID_BLOCK };
struct Disk {
Disk(Byte *f, Size n): file(f), blocks(n) {}
Byte *file;
Size blocks;
struct mem_accessor_t {
MemDevice* md;
Addr addr;
};
Size wordSize, blockSize;
Core &core;
std::vector <Disk> disks;
};
class MemoryUnit {
public:
MemoryUnit(Size pageSize, Size addrBytes, bool disableVm = false) :
pageSize(pageSize), addrBytes(addrBytes), ad(), disableVm(disableVm)
{
if (!disableVm)
tlb[0] = TLBEntry(0, 077);
}
void attach(MemDevice &m, Addr base);
//Size wordSize();
struct PageFault {
PageFault(Addr a, bool nf) : faultAddr(a), notFound(nf) {}
Addr faultAddr;
bool notFound;
}; /* Thrown on page fault. */
Word read(Addr, bool sup); /* For data accesses. */
Word fetch(Addr, bool sup); /* For instruction accesses. */
Byte *getPtr(Addr, Size);
void write(Addr, Word, bool sup, Size);
void tlbAdd(Addr virt, Addr phys, Word flags);
void tlbRm(Addr va);
void tlbFlush() { tlb.clear(); }
private:
class ADecoder {
public:
ADecoder() : zeroChild(NULL), oneChild(NULL), range(0), md(nullptr) {}
ADecoder(MemDevice &md, Size range) :
zeroChild(NULL), oneChild(NULL), range(range), md(&md) {}
Byte *getPtr(Addr a, Size sz, Size wordSize);
Word read(Addr a, bool sup, Size wordSize);
void write(Addr a, Word w, bool sup, Size wordSize);
void map(Addr a, MemDevice &md, Size range, Size bit);
private:
MemDevice &doLookup(Addr a, Size &bit);
ADecoder *zeroChild, *oneChild;
Size range;
MemDevice *md;
struct entry_t {
MemDevice *md;
Addr start;
Addr end;
};
struct TLBEntry {
TLBEntry() {}
TLBEntry(Word pfn, Word flags): pfn(pfn), flags(flags) {}
Word pfn;
Word flags;
};
bool lookup(Addr a, Size wordSize, mem_accessor_t*);
Size pageSize, addrBytes;
ADecoder ad;
std::unordered_map<Addr, TLBEntry> tlb;
TLBEntry tlbLookup(Addr vAddr, Word flagMask);
bool disableVm;
std::vector<entry_t> entries_;
};
class RAM : public MemDevice {
public:
uint8_t* mem[1 << 12];
RAM(){
for(uint32_t i = 0;i < (1 << 12);i++)
mem[i] = NULL;
}
~RAM(){
for(uint32_t i = 0;i < (1 << 12);i++)
if(mem[i])
delete [] mem[i];
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
if(mem[i])
{
delete mem[i];
mem[i] = NULL;
}
}
}
uint8_t* get(uint32_t address){
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0xaa;
ptr[i + 1] = 0xbb;
ptr[i + 2] = 0xcc;
ptr[i + 3] = 0xdd;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
data[i] = (*this)[address + i];
}
}
void write(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
(*this)[address + i] = data[i];
}
}
virtual Size size() const { return -1; }
void getBlock(uint32_t address, uint8_t *data)
{
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t * data)
{
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
// std::cout << std::hex;
// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << (uint32_t) first << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << (uint32_t) second << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << (uint32_t) third << "\n";
// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << (uint32_t) fourth << "\n";
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
// data[0] = (data[0] << 0) | first;
// data[0] = (data[0] << 8) | second;
// data[0] = (data[0] << 8) | third;
// data[0] = (data[0] << 8) | fourth;
// std::cout << "FINAL DATA: " << data[0] << "\n";
}
void writeWord(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t& operator [](uint32_t address) {
return *get(address);
}
virtual void write(Addr addr, Word w)
{
uint32_t word = (uint32_t) w;
writeWord(addr, &word);
}
virtual Word read(Addr addr)
{
uint32_t w;
getWord(addr, &w);
// std::cout << "RAM: read -> " << w << " at addr: " << addr << "\n";
return (Word) w;
}
virtual Byte *base()
{
return (Byte *) this->get(0);
}
// MEMORY UTILS
void loadHexImpl(std::string path);
struct TLBEntry {
TLBEntry() {}
TLBEntry(Word pfn, Word flags)
: pfn(pfn)
, flags(flags)
{}
Word pfn;
Word flags;
};
}
TLBEntry tlbLookup(Addr vAddr, Word flagMask);
std::unordered_map<Addr, TLBEntry> tlb_;
Size pageSize_;
Size addrBytes_;
ADecoder decoder_;
bool disableVm_;
};
///////////////////////////////////////////////////////////////////////////////
class RAM : public MemDevice {
public:
RAM(uint32_t num_pages, uint32_t page_size);
~RAM();
void clear();
Size size() const override;
void write(Addr addr, Word w) override;
Word read(Addr addr) override;
Byte *base() override;
void read(uint32_t address, uint32_t length, uint8_t *data);
void write(uint32_t address, uint32_t length, uint8_t *data);
void writeWord(uint32_t address, uint32_t *data);
void writeHalf(uint32_t address, uint32_t *data);
void writeByte(uint32_t address, uint32_t *data);
void loadHexImage(std::string path);
private:
uint8_t *get(uint32_t address);
void getBlock(uint32_t address, uint8_t *data);
void getWord(uint32_t address, uint32_t *data);
std::vector<uint8_t*> mem_;
uint32_t page_bits_;
uint32_t size_;
};
} // namespace vortex

2
simX/types.h
View File

@@ -14,6 +14,8 @@ typedef uint32_t Size;
typedef std::bitset<32> ThreadMask;
typedef std::bitset<32> WarpMask;
enum MemFlags {
RD_USR = 1,
WR_USR = 2,

8
simX/util.h
View File

@@ -10,6 +10,14 @@ void unused(Args&&...) {}
#define __unused(...) unused(__VA_ARGS__)
constexpr bool ispow2(uint32_t value) {
return value && !(value & (value - 1));
}
constexpr unsigned log2ceil(uint32_t value) {
return 32 - __builtin_clz(value - 1);
}
Word signExt(Word w, Size bit, Word mask);
Word bytesToWord(const Byte *b, Size wordSize);

5
simX/warp.cpp
View File

@@ -24,8 +24,7 @@ Warp::Warp(Core *core, Word id)
iRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
fRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
vRegFile_.resize(core_->arch().num_regs(), std::vector<Byte>(core_->arch().vsize(), 0));
csrs_.resize(core_->arch().num_csrs());
vRegFile_.resize(core_->arch().num_regs(), std::vector<Byte>(core_->arch().vsize(), 0));
}
void Warp::step(trace_inst_t *trace_inst) {
@@ -49,7 +48,7 @@ void Warp::step(trace_inst_t *trace_inst) {
unsigned fetchSize = 4;
fetchBuffer.resize(fetchSize);
Word fetched = core_->mem().fetch(PC_ + fetchPos, 0);
Word fetched = core_->icache_fetch(PC_ + fetchPos, 0);
writeWord(fetchBuffer, fetchPos, fetchSize, fetched);
decPos = 0;

12
simX/warp.h
View File

@@ -44,11 +44,17 @@ public:
Warp(Core *core, Word id = 0);
bool active() const {
return tmask_.any();
return active_;
}
void activate() {
active_ = true;
}
std::size_t getActiveThreads() const {
return tmask_.count();
if (active_)
return tmask_.count();
return 0;
}
void printStats() const;
@@ -71,6 +77,7 @@ public:
void setTmask(size_t index, bool value) {
tmask_[index] = value;
active_ = tmask_.any();
}
void step(trace_inst_t *);
@@ -89,7 +96,6 @@ private:
std::vector<std::vector<Word>> iRegFile_;
std::vector<std::vector<Word>> fRegFile_;
std::vector<std::vector<Byte>> vRegFile_;
std::vector<Word> csrs_;
std::stack<DomStackEntry> domStack_;
struct vtype vtype_;