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rebase master update

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This commit is contained in:
Blaise Tine
2021-07-30 21:03:14 -07:00
parent 79fd92a1b4
commit bb1ceffadd
86 changed files with 6111 additions and 132 deletions
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4
hw/rtl/cache/VX_bank.v vendored
View File

@@ -253,7 +253,7 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
assign {debug_pc_st0, debug_wid_st0} = tag_st0[`CACHE_REQ_INFO_RNG];
end else begin
assign {debug_pc_st0, debug_wid_st0} = 0;
end
@@ -322,7 +322,7 @@ module VX_bank #(
`ifdef DBG_CACHE_REQ_INFO
if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
assign {debug_pc_st1, debug_wid_st1} = tag_st1[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
assign {debug_pc_st1, debug_wid_st1} = tag_st1[`CACHE_REQ_INFO_RNG];
end else begin
assign {debug_pc_st1, debug_wid_st1} = 0;
end

12
hw/rtl/cache/VX_cache_define.vh vendored
View File

@@ -1,5 +1,5 @@
`ifndef VX_CACHE_CONFIG
`define VX_CACHE_CONFIG
`ifndef VX_CACHE_DEFINE
`define VX_CACHE_DEFINE
`include "VX_platform.vh"
@@ -51,17 +51,19 @@
`define LINE_TAG_ADDR(x) x[`LINE_ADDR_WIDTH-1 : `LINE_SELECT_BITS]
`define CACHE_REQ_INFO_RNG CORE_TAG_WIDTH-1:(CORE_TAG_WIDTH-`NW_BITS-32)
///////////////////////////////////////////////////////////////////////////////
`define CORE_RSP_TAGS ((CORE_TAG_ID_BITS != 0) ? 1 : NUM_REQS)
`define BANK_READY_COUNT ((SHARED_BANK_READY != 0) ? 1 : NUM_BANKS)
`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET]
`define MEM_ADDR_BANK(x) x[`BANK_SELECT_BITS+BANK_ADDR_OFFSET-1 : BANK_ADDR_OFFSET]
`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS]
`define MEM_TO_LINE_ADDR(x) x[`MEM_ADDR_WIDTH-1 : `BANK_SELECT_BITS]
`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_MEM_ADDR(x, i) {x, `BANK_SELECT_BITS'(i)}
`define LINE_TO_BYTE_ADDR(x, i) {x, (32-$bits(x))'(i << (32-$bits(x)-`BANK_SELECT_BITS))}

2
hw/rtl/cache/VX_shared_mem.v vendored
View File

@@ -328,7 +328,7 @@ module VX_shared_mem #(
end else begin
$display("%t: cache%0d:%0d core-rd-rsp: addr=%0h, tag=%0h, byteen=%b, data=%0h, wid=%0d, PC=%0h",
$time, CACHE_ID, i, per_bank_core_req_addr[i], per_bank_core_req_tag[i], per_bank_core_req_byteen[i], per_bank_core_rsp_data[i],
debug_wid_st1[i], debug_pc_st1[i]);
debug_wid_st1[i], debug_pc_st1[i]);
end
end
end