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Mrvq stopping reqq popping added to avoid mrvq full deadlock

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This commit is contained in:
felsabbagh3
2020-03-29 13:19:06 -07:00
parent f43a9ad1a6
commit cd418a1f96
2 changed files with 6 additions and 3 deletions
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4
rtl/VX_cache/VX_bank.v
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@@ -218,6 +218,7 @@ module VX_bank
wire mrvq_pop;
wire mrvq_full;
wire mrvq_stop;
wire mrvq_valid_st0;
wire[`vx_clog2(NUMBER_REQUESTS)-1:0] mrvq_tid_st0;
wire [31:0] mrvq_addr_st0;
@@ -279,6 +280,7 @@ module VX_bank
.miss_add_mem_write (miss_add_mem_write),
.miss_add_pc (miss_add_pc),
.miss_resrv_full (mrvq_full),
.miss_resrv_stop (mrvq_stop),
// Broadcast
.is_fill_st1 (is_fill_st2),
@@ -321,7 +323,7 @@ module VX_bank
assign mrvq_pop = mrvq_valid_st0 && !stall_bank_pipe && !mrvq_hazard_st0;
assign dfpq_pop = !mrvq_pop && !dfpq_empty && !stall_bank_pipe && !dfpq_hazard_st0;
assign reqq_pop = !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
assign reqq_pop = !mrvq_stop && !mrvq_pop && !dfpq_pop && !reqq_empty && reqq_req_st0 && !stall_bank_pipe && !is_fill_st1[0] && !(reqq_hazard_st0 || (mrvq_valid_st0 && mrvq_hazard_st0)) && !is_fill_in_pipe;
assign snrq_pop = !reqq_pop && !reqq_pop && !mrvq_pop && !dfpq_pop && snrq_valid_st0 && !stall_bank_pipe && !snrq_hazard_st0;
integer st1_cycle;

5
rtl/VX_cache/VX_cache_miss_resrv.v
View File

@@ -61,6 +61,7 @@ module VX_cache_miss_resrv
input wire[2:0] miss_add_mem_write,
input wire[31:0] miss_add_pc,
output wire miss_resrv_full,
output wire miss_resrv_stop,
// Broadcast Fill
input wire is_fill_st1,
@@ -94,8 +95,8 @@ module VX_cache_miss_resrv
// assign miss_resrv_full = (MRVQ_SIZE != 2) && (tail_ptr+1) == head_ptr;
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE);
assign miss_resrv_full = (MRVQ_SIZE != 2) && (size == MRVQ_SIZE );
assign miss_resrv_stop = (MRVQ_SIZE != 2) && (size == (MRVQ_SIZE-4));
wire enqueue_possible = !miss_resrv_full;
wire[`vx_clog2(MRVQ_SIZE)-1:0] enqueue_index = tail_ptr;