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Updated the two-port GPR model

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This commit is contained in:
Lingjun Zhu
2019-10-13 19:52:14 -04:00
parent 8af8c67299
commit d5dad1c442
2 changed files with 15 additions and 8 deletions
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16
rtl/VX_gpr.v
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@@ -20,11 +20,19 @@ module VX_gpr (
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
.q1 (out_a_reg_data)
);
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_b_reg_data)
);
@@ -81,4 +89,4 @@ module VX_gpr (
// end
endmodule
endmodule

7
rtl/byte_enabled_simple_dual_port_ram.v
View File

@@ -5,10 +5,10 @@
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input wire[4:0] waddr, raddr1, raddr2,
input wire[4:0] waddr, raddr1,
input wire[`NT_M1:0] be,
input wire[`NT_M1:0][31:0] wdata,
output reg[`NT_M1:0][31:0] q1, q2
output reg[`NT_M1:0][31:0] q1
);
// integer regi;
@@ -43,9 +43,8 @@ module byte_enabled_simple_dual_port_ram
end
assign q1 = GPR[raddr1];
assign q2 = GPR[raddr2];
// assign q1 = (raddr1 == waddr && (we)) ? wdata : GPR[raddr1];
// assign q2 = (raddr2 == waddr && (we)) ? wdata : GPR[raddr2];
endmodule
endmodule