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Synthesis Compatible

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Lyons, Ethan Tyler
2019-11-21 21:41:11 -05:00
committed by GitHub Enterprise
parent b4ebc803f3
commit e56e42c8c3
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rtl/modelsim/Makefile
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@@ -7,6 +7,7 @@ SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../VX_define.v \
../VX_define_synth.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \