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OUTPUT_REG refactoring

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This commit is contained in:
Blaise Tine
2021-07-23 06:58:37 -07:00
parent 4ffbcb336f
commit ea1e0f201e
12 changed files with 78 additions and 76 deletions
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16
hw/rtl/afu/VX_avs_wrapper.v
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@@ -44,7 +44,7 @@ module VX_avs_wrapper #(
);
localparam BANK_ADDRW = `LOG2UP(NUM_BANKS);
localparam BUFFERED_OUTPUT = (NUM_BANKS > 2);
localparam OUTPUT_REG = (NUM_BANKS > 2);
// Requests handling
@@ -80,9 +80,9 @@ module VX_avs_wrapper #(
`UNUSED_VAR (req_queue_size)
VX_fifo_queue #(
.DATAW (REQ_TAG_WIDTH),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (!BUFFERED_OUTPUT)
.DATAW (REQ_TAG_WIDTH),
.SIZE (RD_QUEUE_SIZE),
.OUTPUT_REG (!OUTPUT_REG)
) rd_req_queue (
.clk (clk),
.reset (reset),
@@ -124,9 +124,9 @@ module VX_avs_wrapper #(
for (genvar i = 0; i < NUM_BANKS; i++) begin
VX_fifo_queue #(
.DATAW (AVS_DATA_WIDTH),
.SIZE (RD_QUEUE_SIZE),
.BUFFERED (!BUFFERED_OUTPUT)
.DATAW (AVS_DATA_WIDTH),
.SIZE (RD_QUEUE_SIZE),
.OUTPUT_REG (OUTPUT_REG)
) rd_rsp_queue (
.clk (clk),
.reset (reset),
@@ -151,7 +151,7 @@ module VX_avs_wrapper #(
VX_stream_arbiter #(
.NUM_REQS (NUM_BANKS),
.DATAW (AVS_DATA_WIDTH + REQ_TAG_WIDTH),
.BUFFERED (BUFFERED_OUTPUT)
.BUFFERED (OUTPUT_REG ? 1 : 0)
) rsp_arb (
.clk (clk),
.reset (reset),

6
hw/rtl/afu/vortex_afu.sv
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@@ -739,9 +739,9 @@ always @(posedge clk) begin
end
VX_fifo_queue #(
.DATAW (CCI_RD_QUEUE_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE),
.BUFFERED (1)
.DATAW (CCI_RD_QUEUE_DATAW),
.SIZE (CCI_RD_QUEUE_SIZE),
.OUTPUT_REG (1)
) cci_rd_req_queue (
.clk (clk),
.reset (reset),

6
hw/rtl/cache/VX_bank.v vendored
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@@ -111,9 +111,9 @@ module VX_bank #(
wire creq_out_valid, creq_out_ready;
VX_elastic_buffer #(
.DATAW (CORE_TAG_WIDTH + 1 + `LINE_ADDR_WIDTH + (1 + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.SIZE (CREQ_SIZE),
.BUFFERED (CREQ_SIZE > 2)
.DATAW (CORE_TAG_WIDTH + 1 + `LINE_ADDR_WIDTH + (1 + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
.SIZE (CREQ_SIZE),
.OUTPUT_REG (CREQ_SIZE > 2)
) core_req_queue (
.clk (clk),
.reset (reset),

6
hw/rtl/cache/VX_cache.v vendored
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@@ -250,9 +250,9 @@ module VX_cache #(
assign mem_rsp_tag_nc_a = mem_rsp_tag_nc[NC_ENABLE +: `MEM_ADDR_WIDTH];
VX_elastic_buffer #(
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.BUFFERED (MRSQ_SIZE > 2)
.DATAW (`MEM_ADDR_WIDTH + `CACHE_LINE_WIDTH),
.SIZE (MRSQ_SIZE),
.OUTPUT_REG (MRSQ_SIZE > 2)
) mem_rsp_queue (
.clk (clk),
.reset (reset),

6
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -135,9 +135,9 @@ module VX_shared_mem #(
end
VX_elastic_buffer #(
.DATAW (NUM_BANKS * (1 + 1 + `LINE_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS)),
.SIZE (CREQ_SIZE),
.BUFFERED (1) // output should be registered for the data_store addr port
.DATAW (NUM_BANKS * (1 + 1 + `LINE_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS)),
.SIZE (CREQ_SIZE),
.OUTPUT_REG (1) // output should be registered for the data_store addr port
) core_req_queue (
.clk (clk),
.reset (reset),

20
hw/rtl/libs/VX_dp_ram.v
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@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_dp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] waddr,
@@ -24,7 +24,7 @@ module VX_dp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
@@ -93,7 +93,7 @@ module VX_dp_ram #(
end
end
end else begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin

20
hw/rtl/libs/VX_elastic_buffer.v
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@@ -1,10 +1,10 @@
`include "VX_platform.vh"
module VX_elastic_buffer #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter BUFFERED = 0,
parameter FASTRAM = 0
parameter DATAW = 1,
parameter SIZE = 2,
parameter OUTPUT_REG = 0,
parameter FASTRAM = 0
) (
input wire clk,
input wire reset,
@@ -31,8 +31,8 @@ module VX_elastic_buffer #(
end else if (SIZE == 2) begin
VX_skid_buffer #(
.DATAW (DATAW),
.USE_FASTREG (BUFFERED)
.DATAW (DATAW),
.OUTPUT_REG (OUTPUT_REG)
) queue (
.clk (clk),
.reset (reset),
@@ -52,10 +52,10 @@ module VX_elastic_buffer #(
wire pop = valid_out && ready_out;
VX_fifo_queue #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (BUFFERED),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (OUTPUT_REG),
.FASTRAM (FASTRAM)
) queue (
.clk (clk),
.reset (reset),

40
hw/rtl/libs/VX_fifo_queue.v
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@@ -1,14 +1,14 @@
`include "VX_platform.vh"
module VX_fifo_queue #(
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter BUFFERED = 0,
parameter FASTRAM = 1
parameter DATAW = 1,
parameter SIZE = 2,
parameter ALM_FULL = (SIZE - 1),
parameter ALM_EMPTY = 1,
parameter ADDRW = $clog2(SIZE),
parameter SIZEW = $clog2(SIZE+1),
parameter OUTPUT_REG = 0,
parameter FASTRAM = 1
) (
input wire clk,
input wire reset,
@@ -104,7 +104,7 @@ module VX_fifo_queue #(
if (SIZE == 2) begin
if (0 == BUFFERED) begin
if (0 == OUTPUT_REG) begin
reg [DATAW-1:0] shift_reg [1:0];
@@ -139,7 +139,7 @@ module VX_fifo_queue #(
end else begin
if (0 == BUFFERED) begin
if (0 == OUTPUT_REG) begin
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;
@@ -155,11 +155,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),
@@ -200,11 +200,11 @@ module VX_fifo_queue #(
end
VX_dp_ram #(
.DATAW (DATAW),
.SIZE (SIZE),
.BUFFERED (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
.DATAW (DATAW),
.SIZE (SIZE),
.OUTPUT_REG (0),
.RWCHECK (1),
.FASTRAM (FASTRAM)
) dp_ram (
.clk(clk),
.waddr(wr_ptr_r),

4
hw/rtl/libs/VX_skid_buffer.v
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@@ -4,7 +4,7 @@ module VX_skid_buffer #(
parameter DATAW = 1,
parameter PASSTHRU = 0,
parameter NOBACKPRESSURE = 0,
parameter USE_FASTREG = 0
parameter OUTPUT_REG = 0
) (
input wire clk,
input wire reset,
@@ -50,7 +50,7 @@ module VX_skid_buffer #(
end else begin
if (USE_FASTREG) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] buffer;

20
hw/rtl/libs/VX_sp_ram.v
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@@ -2,14 +2,14 @@
`TRACING_OFF
module VX_sp_ram #(
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter BUFFERED = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
parameter DATAW = 1,
parameter SIZE = 1,
parameter BYTEENW = 1,
parameter OUTPUT_REG = 0,
parameter RWCHECK = 1,
parameter ADDRW = $clog2(SIZE),
parameter FASTRAM = 0,
parameter INITZERO = 0
) (
input wire clk,
input wire [ADDRW-1:0] addr,
@@ -23,7 +23,7 @@ module VX_sp_ram #(
`STATIC_ASSERT((1 == BYTEENW) || ((BYTEENW > 1) && 0 == (BYTEENW % 4)), ("invalid parameter"))
if (FASTRAM) begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin
@@ -91,7 +91,7 @@ module VX_sp_ram #(
end
end
end else begin
if (BUFFERED) begin
if (OUTPUT_REG) begin
reg [DATAW-1:0] dout_r;
if (BYTEENW > 1) begin

5
hw/rtl/libs/VX_stream_arbiter.v
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@@ -94,8 +94,9 @@ module VX_stream_arbiter #(
);
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),

5
hw/rtl/libs/VX_stream_demux.v
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@@ -39,8 +39,9 @@ module VX_stream_demux #(
for (genvar i = 0; i < NUM_REQS; i++) begin
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
.DATAW (DATAW),
.PASSTHRU (0 == BUFFERED),
.OUTPUT_REG (2 == BUFFERED)
) out_buffer (
.clk (clk),
.reset (reset),