Interface Checkpoint 2 - Remove Lints
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felsabbagh3
123
rtl/VX_execute.v
123
rtl/VX_execute.v
@@ -2,52 +2,44 @@
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`include "VX_define.v"
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module VX_execute (
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input wire[4:0] in_rd,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_a_reg_data[`NT_M1:0],
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input wire[31:0] in_b_reg_data[`NT_M1:0],
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input wire[4:0] in_alu_op,
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input wire[1:0] in_wb,
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input wire in_rs2_src, // NEW
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input wire[31:0] in_itype_immed, // new
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input wire[2:0] in_mem_read, // NEW
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input wire[2:0] in_mem_write, // NEW
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input wire[31:0] in_PC_next,
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input wire[2:0] in_branch_type,
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input wire[19:0] in_upper_immed,
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input wire[11:0] in_csr_address, // done
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input wire in_is_csr, // done
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input wire[31:0] in_csr_data, // done
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input wire[31:0] in_csr_mask, // done
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input wire in_jal,
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input wire[31:0] in_jal_offset,
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input wire[31:0] in_curr_PC,
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input wire in_valid[`NT_M1:0],
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input [`NW_M1:0] in_warp_num,
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VX_frE_to_bckE_req_inter VX_bckE_req,
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input wire[31:0] in_csr_data,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output reg[31:0] out_csr_result,
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output reg[31:0] out_alu_result[`NT_M1:0],
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output wire[4:0] out_rd,
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output wire[1:0] out_wb,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_a_reg_data[`NT_M1:0],
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output wire[31:0] out_b_reg_data[`NT_M1:0],
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output wire[2:0] out_mem_read,
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output wire[2:0] out_mem_write,
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output wire out_jal,
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output wire[31:0] out_jal_dest,
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output wire[31:0] out_branch_offset,
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output wire out_branch_stall,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0],
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output wire[`NW_M1:0] out_warp_num
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VX_mem_req_inter VX_exe_mem_req,
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output wire[11:0] out_csr_address,
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output wire out_is_csr,
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output reg[31:0] out_csr_result,
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output wire[`NT_M1:0][31:0] out_a_reg_data,
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output wire[`NT_M1:0][31:0] out_b_reg_data,
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output wire out_jal,
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output wire[31:0] out_jal_dest,
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output wire out_branch_stall
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);
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wire[`NT_M1:0][31:0] in_a_reg_data;
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wire[`NT_M1:0][31:0] in_b_reg_data;
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wire[4:0] in_alu_op;
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wire in_rs2_src;
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wire[31:0] in_itype_immed;
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wire[2:0] in_branch_type;
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wire[19:0] in_upper_immed;
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wire[31:0] in_csr_mask;
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wire in_jal;
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wire[31:0] in_jal_offset;
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wire[31:0] in_curr_PC;
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assign in_a_reg_data = VX_bckE_req.a_reg_data;
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assign in_b_reg_data = VX_bckE_req.b_reg_data;
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assign in_alu_op = VX_bckE_req.alu_op;
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assign in_rs2_src = VX_bckE_req.rs2_src;
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assign in_itype_immed = VX_bckE_req.itype_immed;
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assign in_branch_type = VX_bckE_req.branch_type;
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assign in_upper_immed = VX_bckE_req.upper_immed;
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assign in_csr_mask = VX_bckE_req.csr_mask;
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assign in_jal = VX_bckE_req.jal;
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assign in_jal_offset = VX_bckE_req.jal_offset;
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assign in_curr_PC = VX_bckE_req.curr_PC;
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genvar index_out_reg;
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generate
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@@ -63,18 +55,11 @@ module VX_execute (
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.in_alu_op (in_alu_op),
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.in_csr_data (in_csr_data),
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.in_curr_PC (in_curr_PC),
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.out_alu_result(out_alu_result[index_out_reg])
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.out_alu_result(VX_exe_mem_req.alu_result[index_out_reg])
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);
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end
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endgenerate
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// always @(*) begin
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// if ((in_alu_op == `MUL) && (in_warp_num == 1)) begin
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// $display("@PC: %h ---> %d * %d = %d\t%d * %d = %d", in_curr_PC, in_a_reg_data[0], in_b_reg_data[0], out_alu_result[0], in_a_reg_data[1], in_b_reg_data[1], out_alu_result[1]);
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// end
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// end
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assign out_jal_dest = $signed(in_a_reg_data[0]) + $signed(in_jal_offset);
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assign out_jal = in_jal;
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@@ -97,20 +82,30 @@ module VX_execute (
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assign out_rd = in_rd;
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assign out_wb = in_wb;
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assign out_mem_read = in_mem_read;
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assign out_mem_write = in_mem_write;
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assign out_rs1 = in_rs1;
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assign out_a_reg_data = in_a_reg_data;
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assign out_b_reg_data = in_b_reg_data;
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assign out_rs2 = in_rs2;
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assign out_PC_next = in_PC_next;
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assign out_is_csr = in_is_csr;
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assign out_csr_address = in_csr_address;
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assign out_branch_offset = in_itype_immed;
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assign out_valid = in_valid;
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assign out_warp_num = in_warp_num;
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genvar ind;
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for (ind = 0; ind <= `NT_M1; ind = ind + 1) begin
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assign out_a_reg_data[ind] = in_a_reg_data[ind];
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assign out_b_reg_data[ind] = in_b_reg_data[ind];
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end
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assign VX_exe_mem_req.mem_read = VX_bckE_req.mem_read;
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assign VX_exe_mem_req.mem_write = VX_bckE_req.mem_write;
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assign VX_exe_mem_req.wb = VX_bckE_req.wb;
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assign VX_exe_mem_req.rs1 = VX_bckE_req.rs1;
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assign VX_exe_mem_req.rs2 = VX_bckE_req.rs2;
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assign VX_exe_mem_req.rd = VX_bckE_req.rd;
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assign VX_exe_mem_req.rd2 = VX_bckE_req.b_reg_data;
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assign VX_exe_mem_req.wb = VX_bckE_req.wb;
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assign VX_exe_mem_req.PC_next = VX_bckE_req.PC_next;
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assign VX_exe_mem_req.curr_PC = VX_bckE_req.curr_PC;
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assign VX_exe_mem_req.branch_offset = VX_bckE_req.itype_immed;
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assign VX_exe_mem_req.branch_type = VX_bckE_req.branch_type;
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assign VX_exe_mem_req.valid = VX_bckE_req.valid;
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assign VX_exe_mem_req.warp_num = VX_bckE_req.warp_num;
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assign out_is_csr = VX_bckE_req.is_csr;
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assign out_csr_address = VX_bckE_req.csr_address;
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endmodule // VX_execute
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