Interface Checkpoint 2 - Remove Lints

rtl/VX_writeback.v

@@ -6,26 +6,24 @@ module VX_writeback (
 		/* verilator lint_off UNUSED */
 		input wire       clk,
 		/* verilator lint_off UNUSED */
-		input wire[31:0] in_alu_result[`NT_M1:0],
-		input wire[31:0] in_mem_result[`NT_M1:0],
+		input wire[`NT_M1:0][31:0] in_alu_result,
+		input wire[`NT_M1:0][31:0] in_mem_result,
 		input wire[4:0]  in_rd,
 		input wire[1:0]  in_wb,
 		input wire[31:0] in_PC_next,
 		/* verilator lint_off UNUSED */
-		input wire       in_valid[`NT_M1:0],
+		input wire[`NT_M1:0]       in_valid,
 		/* verilator lint_on UNUSED */
 		input wire [`NW_M1:0]  in_warp_num,
 
-		output wire[31:0] out_write_data[`NT_M1:0],
-		output wire[4:0] out_rd,
-		output wire[1:0] out_wb,
-		output wire[`NW_M1:0]  out_warp_num
+
+		VX_wb_inter       VX_writeback_inter
 	);
 
 		wire is_jal;
 		wire uses_alu;
 
-		wire[31:0] out_pc_data[`NT_M1:0];
+		wire[`NT_M1:0][31:0] out_pc_data;
 
 
 		// genvar index;
@@ -49,20 +47,14 @@ module VX_writeback (
 		assign is_jal   = in_wb == `WB_JAL;
 		assign uses_alu = in_wb == `WB_ALU;
 
-		assign out_write_data = is_jal ? out_pc_data :
+		assign VX_writeback_inter.write_data = is_jal ? out_pc_data :
 										uses_alu ? in_alu_result :
 													in_mem_result;
 
-
-		// always @(negedge clk) begin
-		// 	if (in_wb != 0)  begin
-		// 		$display("[%h] WB Data: %h {%h}, to register: %d [%d %d]",in_PC_next - 4, out_write_data[0], in_mem_result[0], in_rd, in_valid[0], in_valid[1]);
-		// 	end
-		// end
-
-		assign out_rd = in_rd;
-		assign out_wb = in_wb;
-		assign out_warp_num = in_warp_num;
+		assign VX_writeback_inter.wb_valid    = in_valid;
+		assign VX_writeback_inter.rd          = in_rd;
+		assign VX_writeback_inter.wb          = in_wb;
+		assign VX_writeback_inter.wb_warp_num = in_warp_num;
 
 
 endmodule // VX_writeback