felsabbagh3
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13c6cbfa5d
|
L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
|
cf0173ae15
|
Fixed Stall Pipeline Logic
|
2020-03-09 22:08:46 -07:00 |
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felsabbagh3
|
e2ffbcf14b
|
MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
|
felsabbagh3
|
a539630a0a
|
Added Vortex SOC
|
2020-03-08 15:24:21 -07:00 |
|
felsabbagh3
|
b5b04a7070
|
Added Shared Memory
|
2020-03-08 15:00:53 -07:00 |
|
felsabbagh3
|
b9a95631bc
|
Icache stage mods + removed shared memory
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2020-03-08 14:04:55 -07:00 |
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felsabbagh3
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2f94b26af0
|
Icache working
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2020-03-08 13:59:35 -07:00 |
|
felsabbagh3
|
507d20f413
|
Cache Working on Mem Copy
|
2020-03-08 01:55:15 -08:00 |
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felsabbagh3
|
f03f3fe037
|
Fixed all Cache Warnings
|
2020-03-07 14:34:05 -08:00 |
|
Blaise Tine
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3953a71180
|
fixed write logic in generic_queue_ll
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2020-03-07 06:56:11 -05:00 |
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felsabbagh3
|
9bf0add937
|
Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
|
fb23812e95
|
Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
|
44f6c68fe9
|
Got queue_ll to work by modifying when to update bypass
|
2020-03-06 22:50:20 -08:00 |
|
Blaise Tine
|
0816426662
|
added unit_test
|
2020-03-06 10:31:31 -05:00 |
|
Blaise Tine
|
9f5235dc3d
|
added generic_queue_ll
|
2020-03-05 10:43:15 -05:00 |
|
Blaise Tine
|
9c56a10f15
|
synthesis fixes
|
2020-03-05 09:11:43 -05:00 |
|
Blaise Tine
|
33868512ac
|
synthesis fixes
|
2020-03-05 07:03:23 -05:00 |
|
Blaise Tine
|
66a46f81ce
|
synthesis fixes
|
2020-03-05 06:58:51 -05:00 |
|
felsabbagh3
|
457e8644f3
|
Added Snoop Invalidate/Writeback Req type
|
2020-03-05 01:30:16 -08:00 |
|
felsabbagh3
|
e0620a6f6a
|
Added fill_invalidator
|
2020-03-04 23:55:02 -08:00 |
|
felsabbagh3
|
b038bdb491
|
New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
|
felsabbagh3
|
b0b9b8238e
|
Passing some cases
|
2020-03-04 04:05:54 -08:00 |
|
felsabbagh3
|
8f001ac6f2
|
Added All Interfaces
|
2020-03-03 22:48:49 -08:00 |
|
felsabbagh3
|
73cecd3866
|
Added Core Interface
|
2020-03-03 22:14:56 -08:00 |
|
felsabbagh3
|
57a96e02b1
|
Fixed some other timing issues
|
2020-03-03 21:15:44 -08:00 |
|
felsabbagh3
|
08986bf1dc
|
Fixed incorrect valid and'ing in execute
|
2020-03-03 20:57:20 -08:00 |
|
felsabbagh3
|
a47f7c11ec
|
Finished cache, dram imp + interfaces left
|
2020-03-03 19:42:33 -08:00 |
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felsabbagh3
|
8ece8d8893
|
Fixed miss reserv to support ST->LD sequences
|
2020-03-03 17:04:39 -08:00 |
|
felsabbagh3
|
80af320fdb
|
Before fixing miss rsrv for ST->LD sequences
|
2020-03-03 16:57:05 -08:00 |
|
felsabbagh3
|
361fc2c3fe
|
Finished st0
|
2020-03-03 02:49:30 -08:00 |
|
felsabbagh3
|
3a970bbe7b
|
Connected cache to bank
|
2020-03-02 23:24:17 -08:00 |
|
felsabbagh3
|
fc5621cd1d
|
Everything except bank internals
|
2020-03-02 23:08:54 -08:00 |
|
felsabbagh3
|
abca2f7abb
|
Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
|
2020-03-01 22:27:18 -08:00 |
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felsabbagh3
|
6bf25b5b78
|
+Added icache stage -- 3rd case of AUIPC os broken?
|
2020-03-01 18:01:02 -08:00 |
|
wgulian3
|
23aabbf01d
|
Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
|
2020-02-22 20:16:13 -05:00 |
|
wgulian3
|
b2afe526fe
|
Update multiply for not SYN_FUNC
|
2020-02-21 23:20:04 -05:00 |
|
wgulian3
|
f2c0453702
|
Add multi-cycle compat module and use it in ALU
|
2020-02-21 22:08:09 -05:00 |
|
wgulian3
|
83d1f54fcf
|
fix shared mem ram inference
|
2020-02-20 15:59:23 -05:00 |
|
wgulian3
|
55d722364d
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-20 02:36:39 -05:00 |
|
codetector
|
e82e29c855
|
remove async reset for FPGA synthesis
|
2020-02-19 23:19:05 -05:00 |
|
wgulian3
|
de85cfd296
|
fix clean build with makefile
|
2020-02-19 17:33:51 -05:00 |
|
Codetector
|
072c89c433
|
Merge branch 'fpga_synthesis' into fix_cache_m10k
|
2020-02-19 16:03:23 -05:00 |
|
wgulian3
|
5dadeffac8
|
fix project.tcl
|
2020-02-19 14:20:58 -05:00 |
|
wgulian3
|
3b60c10460
|
Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis
|
2020-02-19 01:04:55 -05:00 |
|
wgulian3
|
3423e3189f
|
Fix e2e building issues and increase division pipeline length
|
2020-02-19 01:04:48 -05:00 |
|
wgulian3
|
3e68c8bcf5
|
verilator does not support delayed assignment in a loop
|
2020-02-18 13:38:17 -05:00 |
|
wgulian3
|
e76d05f7ce
|
Fix issues quartus synthesis issues
|
2020-02-18 13:24:18 -05:00 |
|
wgulian3
|
d71f8fcc73
|
Fix divide edge case in verilator and move divide modules out of SYN_FUNC block within alu.
|
2020-02-18 13:02:46 -05:00 |
|
wgulian3
|
a32d654263
|
Merge branch 'master' into fpga_synthesis
|
2020-02-18 03:35:12 -05:00 |
|
wgulian3
|
61803741f8
|
Merge branch 'master' into fpga_synthesis
# Conflicts:
# rtl/VX_back_end.v
# rtl/VX_gpr_stage.v
# rtl/VX_writeback.v
# rtl/simulate/test_bench.cpp
# rtl/simulate/test_bench.h
# runtime/mains/dev/Makefile
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2020-02-18 03:34:38 -05:00 |
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