felsabbagh3
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13c6cbfa5d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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cf0173ae15
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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e2ffbcf14b
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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b5b04a7070
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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507d20f413
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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f03f3fe037
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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felsabbagh3
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9bf0add937
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
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fb23812e95
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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44f6c68fe9
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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Blaise Tine
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0816426662
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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9f5235dc3d
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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9c56a10f15
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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33868512ac
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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66a46f81ce
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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457e8644f3
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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e0620a6f6a
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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b038bdb491
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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b0b9b8238e
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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a47f7c11ec
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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8ece8d8893
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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80af320fdb
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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361fc2c3fe
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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3a970bbe7b
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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fc5621cd1d
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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