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1,362 Commits 6 Branches 0 Tags
1595ff08e299e09a5978d09aba7b6ed16ae4913d
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8 Commits

Author SHA1 Message Date
Xandy Liu
1595ff08e2 PERF pipeline stalls and cache 2020-12-08 01:14:41 -05:00
Blaise Tine
d319ae3b97 minor rupdate 2020-10-26 05:27:10 -04:00
Blaise Tine
09b1c0eea7 minor update 2020-10-26 02:02:05 -07:00
Blaise Tine
f6f95e0c46 mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL 2020-09-19 14:45:42 -04:00
MalikBurton
b7da1dbcb8 Reordered make list to make runtime go last 2020-08-15 13:05:15 -04:00
Blaise Tine
c9755a0c48 lkg build with pipeline + FPU fixes 2020-07-31 09:29:44 -04:00
Blaise Tine
9ae38433fb VX_pipeline refactoring + logic analyzer 2020-06-06 01:52:44 -04:00
Blaise Tine
106d707024 verilator suppor for opae (partial) 2020-06-03 06:22:49 -04:00
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