Xandy Liu
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1595ff08e2
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PERF pipeline stalls and cache
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2020-12-08 01:14:41 -05:00 |
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Blaise Tine
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0d0706411d
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CSR IO's critical path elimination
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2020-12-06 16:07:36 -08:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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b677f724aa
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Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit
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2020-12-01 12:37:15 -08:00 |
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Blaise Tine
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74c9e9ad1f
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minor update
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2020-12-01 10:42:14 -08:00 |
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Blaise Tine
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f9d98c5a2b
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fixed bank_core_req_arb critical path.
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2020-12-01 08:47:52 -08:00 |
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Blaise Tine
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5758ef9ebf
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generic_register reset network optimization
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2020-11-29 18:41:36 -08:00 |
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Blaise Tine
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457f831435
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fixed scoreboard stall
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2020-11-28 03:14:20 -05:00 |
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Blaise Tine
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461be0880d
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fixed FPU-CSR data dependence
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2020-11-25 09:05:38 -08:00 |
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Blaise Tine
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34b650be94
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fixed shared memory addressing critical path, fixed VX_fp_noncomp output bug
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2020-11-17 00:27:24 -08:00 |
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Blaise Tine
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b14007f930
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pipeline optimization: fixed GPR fanout delay to execute units
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2020-11-07 02:01:21 -08:00 |
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Blaise Tine
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5be1d85648
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cache refactoring (fixed redundant fill requests, merged fill and writeback queues), optimized priority encoder, fixed crs cycles count
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2020-11-02 01:50:12 -08:00 |
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Blaise Tine
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32da50816f
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scope refactoring: adding modules definitions to VCD trace
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2020-10-12 23:26:02 -04:00 |
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Blaise Tine
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f6f95e0c46
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mutiple fixes: parallel printf, fixed cycle in cache, opencl refactored vecadd and sgemm, regen opencl kernels with hard-float, fixed vortex io bus interface, fixed dpi floats APi to support multicore mode, make vlsim multicore default, make rtlsim multi-core default, removed POCL binaries from repository, updated Makefiles to use external POCL
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2020-09-19 14:45:42 -04:00 |
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Blaise Tine
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49b86c4b2a
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SCOPE update
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2020-09-05 10:52:59 -07:00 |
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Blaise Tine
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ee81e81818
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adding using serial divider to save area cost
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2020-08-25 02:29:27 -07:00 |
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Blaise Tine
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57971f6c76
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decode op_mod optimization
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2020-08-24 02:55:14 -07:00 |
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Blaise Tine
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f292e5003d
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quartus build fixes
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2020-08-23 22:04:46 -07:00 |
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Blaise Tine
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0b355f228e
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ibuffer addition
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2020-08-22 00:22:04 -07:00 |
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Blaise Tine
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6c12391338
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pipeline refactoring - fmax >= 222 mhz
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2020-08-14 21:50:14 -07:00 |
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Blaise Tine
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c9755a0c48
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lkg build with pipeline + FPU fixes
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2020-07-31 09:29:44 -04:00 |
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Blaise Tine
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8976100025
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floating point support fixes
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2020-07-28 04:19:46 -04:00 |
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Blaise Tine
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e0a9089647
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floating point support fixes
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2020-07-27 16:01:56 -04:00 |
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Blaise Tine
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7c86b68977
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pipeline refactoring: centralized issue buffer
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2020-07-26 11:21:08 -04:00 |
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Blaise Tine
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1f63f9da25
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new fpu implementation
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2020-07-24 00:00:37 -04:00 |
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Blaise Tine
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75e3c31b56
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fpu implementation (part1)
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2020-07-23 03:18:09 -07:00 |
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Blaise Tine
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dc7efbcfb4
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pipeline refactoring
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2020-07-21 05:22:47 -04:00 |
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