 Blaise Tine
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3252d52694
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refactoring RTL simulator and Makefile
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2020-03-26 04:14:36 -04:00 |
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Blaise Tine
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acafcceb94
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fixed Modelsim build errors
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2020-03-26 03:56:44 -04:00 |
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Blaise Tine
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8aa2d74714
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fixed Modelsim build errors
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2020-03-26 03:54:23 -04:00 |
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Blaise Tine
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07c52d8729
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code refactoring
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2020-03-26 03:20:46 -04:00 |
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Blaise Tine
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bf3d1fb5a2
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code refactoring
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2020-03-26 01:41:01 -04:00 |
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felsabbagh3
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5372c07b01
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Fixed most of the cache issues, mat_add left
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2020-03-22 15:59:45 -07:00 |
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felsabbagh3
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82ea79c680
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Fix for Single-Threaded
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2020-03-22 14:44:46 -07:00 |
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wgulian3
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10ebfd7e24
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Add threaded -O3 build mode
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2020-03-21 17:23:40 -04:00 |
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wgulian3
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f565d47844
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revert saxpy change and fix stage_1_cycles not working
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2020-03-20 04:49:02 -04:00 |
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wgulian3
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5b3df797a4
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Add modified RTL files for parameterized builds with VX_define_synth.v
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2020-03-20 04:04:15 -04:00 |
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felsabbagh3
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ff2fc5fa43
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Fixed no L3 Verilator issues
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2020-03-13 15:11:20 -07:00 |
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felsabbagh3
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0f5528a229
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Removed L3 for synthesis
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2020-03-13 15:01:46 -07:00 |
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wgulian3
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07ed4085ae
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Add power analysis Make target
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2020-03-12 13:14:50 -04:00 |
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wgulian3
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c5fe43724e
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replace procedural continuous assignments and force MLAB inference for generic_queue_ll
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2020-03-10 17:46:48 -04:00 |
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wgulian3
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a931b588c2
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minor tweaks to appease quartus
re-add fancy timing analysis scripts and revert to Makefile with custom quartus location support
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2020-03-10 12:15:30 -04:00 |
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felsabbagh3
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ca62e57a0d
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L3 and CLUSTRING WORKS
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2020-03-10 02:41:47 -07:00 |
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felsabbagh3
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dea271eb6b
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Fixed Stall Pipeline Logic
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2020-03-09 22:08:46 -07:00 |
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felsabbagh3
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469334f23e
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MULTICORE WITH L2 WORKING
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2020-03-09 01:17:11 -07:00 |
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felsabbagh3
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24f20a2da4
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Added Vortex SOC
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2020-03-08 15:24:21 -07:00 |
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felsabbagh3
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6c52b3d09b
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Added Shared Memory
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2020-03-08 15:00:53 -07:00 |
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felsabbagh3
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ec1aad1591
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Icache stage mods + removed shared memory
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2020-03-08 14:04:55 -07:00 |
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felsabbagh3
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f315a8a44d
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Icache working
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2020-03-08 13:59:35 -07:00 |
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felsabbagh3
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3b11e1d72f
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Cache Working on Mem Copy
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2020-03-08 01:55:15 -08:00 |
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felsabbagh3
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4ed62f1aad
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Fixed all Cache Warnings
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2020-03-07 14:34:05 -08:00 |
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Blaise Tine
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ddafe96ca6
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fixed write logic in generic_queue_ll
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2020-03-07 06:56:11 -05:00 |
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felsabbagh3
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db11bf6990
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Made the cache module configurable for multi-instantiation
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2020-03-07 00:49:40 -08:00 |
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felsabbagh3
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90d10f4b7d
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Added Lower Level Cache Hit Queue
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2020-03-06 23:04:42 -08:00 |
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felsabbagh3
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2c616d8201
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Got queue_ll to work by modifying when to update bypass
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2020-03-06 22:50:20 -08:00 |
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Blaise Tine
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abfd592fd2
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added unit_test
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2020-03-06 10:31:31 -05:00 |
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Blaise Tine
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730c36ef18
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added generic_queue_ll
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2020-03-05 10:43:15 -05:00 |
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Blaise Tine
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721d22ae86
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synthesis fixes
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2020-03-05 09:11:43 -05:00 |
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Blaise Tine
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2ed98a4764
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synthesis fixes
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2020-03-05 07:03:23 -05:00 |
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Blaise Tine
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369c2c625c
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synthesis fixes
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2020-03-05 06:58:51 -05:00 |
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felsabbagh3
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7222cdd199
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Added Snoop Invalidate/Writeback Req type
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2020-03-05 01:30:16 -08:00 |
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felsabbagh3
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c257c0578e
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Added fill_invalidator
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2020-03-04 23:55:02 -08:00 |
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felsabbagh3
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a86a403ca9
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New Cache Design Passing All Tests
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2020-03-04 23:24:32 -08:00 |
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felsabbagh3
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aa1a0ee376
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Passing some cases
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2020-03-04 04:05:54 -08:00 |
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felsabbagh3
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d8e25045be
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Added All Interfaces
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2020-03-03 22:48:49 -08:00 |
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felsabbagh3
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01ae6ffafe
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Added Core Interface
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2020-03-03 22:14:56 -08:00 |
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felsabbagh3
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58db00f555
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Fixed some other timing issues
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2020-03-03 21:15:44 -08:00 |
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felsabbagh3
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25b6dbdfa8
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Fixed incorrect valid and'ing in execute
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2020-03-03 20:57:20 -08:00 |
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felsabbagh3
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733d00aba9
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Finished cache, dram imp + interfaces left
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2020-03-03 19:42:33 -08:00 |
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felsabbagh3
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e2e053ff7b
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Fixed miss reserv to support ST->LD sequences
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2020-03-03 17:04:39 -08:00 |
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felsabbagh3
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b150327ca9
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Before fixing miss rsrv for ST->LD sequences
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2020-03-03 16:57:05 -08:00 |
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felsabbagh3
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8784b09b18
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Finished st0
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2020-03-03 02:49:30 -08:00 |
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felsabbagh3
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8c6284f627
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Connected cache to bank
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2020-03-02 23:24:17 -08:00 |
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felsabbagh3
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f6cc05eaa2
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Everything except bank internals
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2020-03-02 23:08:54 -08:00 |
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felsabbagh3
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d78338c7d4
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Modified Scheduler to be mask based (allows thread granuility writebacks) + Fixed all LW and SW unit test errors errors
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2020-03-01 22:27:18 -08:00 |
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felsabbagh3
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f98f5c414d
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+Added icache stage -- 3rd case of AUIPC os broken?
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2020-03-01 18:01:02 -08:00 |
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wgulian3
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ca61801199
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Make ALU div/mul pipelines longer and support logic element multiplication mode for better long pipeline performance
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2020-02-22 20:16:13 -05:00 |
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