Blaise Tine
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703d3faf27
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minor bug fixes
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2022-02-05 06:37:54 -05:00 |
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Blaise Tine
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5fbace9fa0
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fixed several bugs and refactor memory access
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2022-02-04 17:50:19 -05:00 |
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Blaise Tine
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cf2a0a5f39
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code refactoring
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2022-02-04 00:07:24 -05:00 |
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Santosh Srivatsan
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836c777680
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XLEN parameterization for simx
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2022-02-03 15:19:31 -05:00 |
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Santosh Srivatsan
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54dd2cfe1d
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Added xlen parameterization to types.h instead of xlen.h
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2022-02-01 14:02:46 -05:00 |
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Santosh Srivatsan
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01d183c6a9
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Removed xlen.h
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2022-02-01 13:59:39 -05:00 |
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Santosh Srivatsan
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3eb2b71955
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removed traces of xlen. Overloaded sext
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2022-02-01 13:54:51 -05:00 |
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Santosh Srivatsan
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a73f656d06
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Minor bug fixes
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2022-01-31 17:01:14 -05:00 |
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Santosh Srivatsan
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4cf596338d
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Minor bug fixes
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2022-01-31 15:53:49 -05:00 |
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Santosh Srivatsan
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7e3a2fdb0f
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Modifications to allow 64-bit riscv tests to run on travis CI
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2022-01-27 15:55:19 -05:00 |
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Santosh Srivatsan
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7aa93a735d
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Added FLEN parameterization for RV32/64 F and D instructions
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2022-01-24 15:42:15 -05:00 |
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Santosh Srivatsan
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ad92c09f5b
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Changed all instances of DWord to XWord and DWordI to XWordI. Added XLEN parameterization to the simx Makefile
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2022-01-22 13:47:44 -05:00 |
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Santosh Srivatsan
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91c22a2592
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Fixed some riscv-tests
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2022-01-22 12:54:10 -05:00 |
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Santosh Srivatsan
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d762d401cd
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Added 64-bit linker script
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2022-01-11 17:22:16 -05:00 |
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Santosh Srivatsan
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f93303bac7
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Minor update
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2021-12-15 17:21:38 -05:00 |
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Santosh Srivatsan
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71acf4eadb
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Changed instruction size from wsize() * 4 to wsize() * 8
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2021-12-13 20:42:44 -05:00 |
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Santosh Srivatsan
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d8796efd89
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Minor update
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2021-12-13 20:39:40 -05:00 |
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Santosh Srivatsan
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b1e82223ee
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Renamed rv_f* functions to rvf*_s to follow the naming convention between single and double precision floating point
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2021-12-13 20:37:29 -05:00 |
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Santosh Srivatsan
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76eb79d7fa
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Removed pipeline.cpp
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2021-12-13 19:57:47 -05:00 |
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Santosh Srivatsan
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4abfca4cb2
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Replaced all instanced of DoubleWord to DWord and DoubleWordI to DWordI
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2021-12-13 19:55:02 -05:00 |
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Santosh Srivatsan
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e82d5fe48f
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Removed all comments labelled \'simx64\'
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2021-12-13 19:52:13 -05:00 |
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Santosh Srivatsan
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67daa6e616
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Minor update
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2021-12-11 17:58:31 -05:00 |
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Santosh Srivatsan
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885bb58ca9
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Merged RV64IMFD extensions to master branch
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2021-12-11 17:06:29 -05:00 |
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Santosh Srivatsan
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3324b32a29
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Moved Dockerfile to miscs
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2021-12-10 21:54:41 -05:00 |
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Santosh Srivatsan
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5edb9098ce
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Merge branch 'simx64'
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2021-12-10 21:48:29 -05:00 |
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Santosh Srivatsan
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e7bc436b52
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Renamed simX to simx
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2021-12-10 16:57:29 -05:00 |
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Santosh Raghav Srivatsan
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bde789b320
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Added support for RV32D and RV64D instructions
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2021-12-10 16:30:24 -05:00 |
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Blaise Tine
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0e2de4f13a
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prefetch test fixes
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2021-12-09 04:54:10 -05:00 |
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Blaise Tine
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5825b7c15a
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dram simulator fix
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2021-12-07 22:44:06 -05:00 |
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Santosh Raghav Srivatsan
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e6eda67d0c
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Modified RV32F instructions to support 64-bit register file and added RV64F ISA extension
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2021-12-06 18:55:13 -05:00 |
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Blaise Tine
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b741807f8c
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using ramulator dram simulator
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2021-12-06 01:22:45 -05:00 |
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Santosh Raghav Srivatsan
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3784da0d2f
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riscv-tests work on simx
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2021-12-01 19:41:16 -05:00 |
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Blaise Tine
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189cec3ca2
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minor update
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2021-12-01 10:36:50 -05:00 |
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Santosh Raghav Srivatsan
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f0dc04ad04
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Added tests to commit. 64 bit simx still not working
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2021-12-01 02:44:14 -05:00 |
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Blaise Tine
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092ff42ab4
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simx multicore fix
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2021-12-01 00:12:16 -05:00 |
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Blaise Tine
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2a7a4df342
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simx directory name fix
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2021-11-30 07:17:58 -05:00 |
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Blaise Tine
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41d7e6c63a
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cummulative fixes, RTL uuid trace, texture unit fixes, simx timing fixes
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2021-11-30 07:08:15 -05:00 |
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Santosh Raghav Srivatsan
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64d47f3637
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Added support for RV64I instructions
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2021-11-27 12:33:30 -05:00 |
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Blaise Tine
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b995843a5b
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cocogfx fixes and refactoring
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2021-11-25 13:58:09 -05:00 |
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Blaise Tine
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a671e1a05d
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moving submodules into third_party folder
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2021-11-24 18:10:00 -05:00 |
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Blaise Tine
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18762dffce
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fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
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2021-11-24 00:00:17 -05:00 |
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Blaise Tine
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27a65fdee7
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driver refactoring
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2021-11-14 09:05:15 -05:00 |
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Blaise Tine
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808bddb586
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simx timing simulation refactoring
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2021-11-14 08:52:34 -05:00 |
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Blaise Tine
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c2721fd545
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SimX timing simulation
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2021-11-13 01:41:12 -05:00 |
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Santosh Raghav Srivatsan
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d1892bd6ec
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Added support for a few RV64I instructions
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2021-11-11 13:35:14 -05:00 |
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Santosh Raghav Srivatsan
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9cd8dec397
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Extended register file to 64 bits
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2021-11-08 17:54:16 -05:00 |
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Blaise Tine
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fe862f64b1
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dispatch refactoring
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2021-10-19 15:16:00 -04:00 |
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Blaise Tine
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e248f744d5
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Merge branch 'master' of https://github.com/vortexgpgpu/vortex
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2021-10-19 03:07:13 -04:00 |
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Blaise Tine
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bf72800676
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debug tracing refactoring
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2021-10-17 13:42:16 -07:00 |
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Blaise Tine
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78345d8bdf
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fixed warning messages
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2021-10-15 21:30:47 -07:00 |
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