Blaise Tine
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9f34b2944c
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code refactoring for Vivado, sv2v, and yosys compatibility
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2021-09-27 08:55:10 -04:00 |
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Blaise Tine
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9b04f3d9d6
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Updated README and synthesis scripts
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2021-09-22 07:50:47 -07:00 |
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Blaise Tine
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ca46b0a0be
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OUTPUT_REG => OUT_REG renaming
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2021-09-09 03:05:38 -07:00 |
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Blaise Tine
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af1cecae07
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stream arbiter update
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2021-09-06 23:38:20 -07:00 |
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Blaise Tine
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fe5112b6c1
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minor updates
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2021-09-05 23:05:21 -07:00 |
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Blaise Tine
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90b50277d0
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cache multi-porting fixes + optimization
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2021-08-29 18:33:49 -07:00 |
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Blaise Tine
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5392395fba
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minor update
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2021-08-28 23:13:50 -07:00 |
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Blaise Tine
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6674e8c44a
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cache bank area optimization + multi-porting fix for l2/l3 caches
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2021-08-28 21:34:06 -07:00 |
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Blaise Tine
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2a27bfbfd5
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LKG Build (reset network update -fmax=236 mhz 4c)
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2021-08-23 01:59:22 -07:00 |
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Blaise Tine
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9098495153
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MSHR Redesign: removed fifo replay constraints and overheads
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2021-08-12 01:49:32 -07:00 |
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Blaise Tine
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6525dff158
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fixed no shared memory bug, fixed cache debug log
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2021-08-02 15:59:33 -07:00 |
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Blaise Tine
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ea1e0f201e
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OUTPUT_REG refactoring
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2021-07-23 06:58:37 -07:00 |
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Blaise Tine
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53b3d42908
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cache's core response queue size control
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2021-07-16 13:09:29 -07:00 |
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Blaise Tine
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d9425cc484
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cache elastic buffer optimization
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2021-07-15 11:59:49 -07:00 |
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Blaise Tine
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8678150ce0
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cache multi-porting optimization
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2021-07-15 11:54:27 -07:00 |
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Blaise Tine
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5c40422e4f
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dcache response bus optimization
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2021-07-12 10:14:48 -07:00 |
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Blaise Tine
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41069ba188
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non-cacheable memory address fixes
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2021-06-06 20:54:36 -07:00 |
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Blaise Tine
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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Blaise Tine
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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Blaise Tine
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04a1c0e9eb
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IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
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2021-05-01 13:44:08 -07:00 |
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Blaise Tine
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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Blaise Tine
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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Blaise Tine
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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Blaise Tine
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04a96e89c9
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minor update
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2021-04-01 12:34:18 -07:00 |
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Blaise Tine
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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Blaise Tine
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111cc29482
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minor update
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2021-02-04 15:28:04 -08:00 |
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Blaise Tine
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62ff97d6e1
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minor update - smem perf update
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2021-02-01 10:29:20 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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a69ba5ad7b
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cache flush support
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2021-01-17 05:50:29 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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a56ecb696d
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minor updates
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2021-01-16 14:05:47 -08:00 |
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Blaise Tine
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fcbf57b66a
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specialized shared memory module
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2021-01-16 04:41:58 -08:00 |
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Blaise Tine
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b4b5d6f0ab
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minor updates
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2021-01-12 15:19:38 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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31ff70fd4e
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minor updates
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2021-01-05 15:03:41 -08:00 |
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Blaise Tine
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9cef1aae04
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cache fill response address is the mshr's top address, no need to store it
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2021-01-03 00:57:24 -05:00 |
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Blaise Tine
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2d69ca5d67
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scratchpad optimization for stack access using custom bank offset aligned to stack size
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2021-01-02 16:00:00 -05:00 |
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Blaise Tine
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abe32ed553
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cache optimization - moved read requests to stage1 and eliminating stage3
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2020-12-31 07:40:58 -08:00 |
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Blaise Tine
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b459192dec
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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Blaise Tine
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703a861fe9
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added support for write-through cache, removed cache snooping support
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2020-12-23 23:51:02 -08:00 |
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Blaise Tine
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d956e268b9
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adding new performance counters (banks utilization and DRAM bus utilization)
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2020-12-22 12:33:45 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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