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38b92ad592
- using SV_DPI defines to disable DPI in synthesis-based simulations
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- fixed Intel ASE run script: run_ase.sh
2024-01-28 00:22:21 -08:00
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43154cf738
minor updates
2023-11-16 23:41:59 -08:00
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d65cc61df5
minor update
2023-11-16 12:00:37 -08:00
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547d916ae2
minor update
2023-11-15 13:00:06 -08:00
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62cdd8e993
minor update
2023-11-11 15:49:39 -08:00
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c1e168fdbe
Vortex 2.0 changes:
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+ Microarchitecture optimizations
+ 64-bit support
+ Xilinx FPGA support
+ LLVM-16 support
+ Refactoring and quality control fixes
minor update
minor update
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cleanup
cleanup
cache bindings and memory perf refactory
minor update
minor update
hw unit tests fixes
minor update
minor update
minor update
minor update
minor update
minor udpate
minor update
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minor updates
minor updates
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minor updates
minor updates
minor updates
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minor update
2023-11-10 02:47:05 -08:00
Blaise Tine
a06812f93f
minor updates
2022-02-01 22:51:33 -05:00
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38f166f090
texture unit hardware optimizations
2021-12-02 10:22:21 -08:00
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b995843a5b
cocogfx fixes and refactoring
2021-11-25 13:58:09 -05:00
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18762dffce
fixes: texture unit mem access sometimes going to smem, bilinear texture filtering; new: cache req_id,
2021-11-24 00:00:17 -05:00
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bf72800676
debug tracing refactoring
2021-10-17 13:42:16 -07:00
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58a2140b92
merge update
2021-10-15 19:58:13 -07:00
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e380ded5e1
Merge branch 'master' into graphics
2021-10-15 19:32:11 -07:00
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e2b5799a01
minor updates
2021-10-13 15:55:35 -04:00
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1cd833d2c4
minor fixes
2021-10-11 19:02:13 -07:00
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28e26f3130
minor update
2021-10-09 13:19:46 -07:00
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54bddeee9c
simulation framework refactoring
2021-10-09 10:20:42 -04:00
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8e82ee00a0
minor update
2021-09-29 09:32:21 -07:00
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bbcb50ba81
minor update
2021-09-29 04:49:36 -04:00
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a45261b530
code refactoring for Vivado compatibility
2021-09-29 03:24:17 -04:00
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9f34b2944c
code refactoring for Vivado, sv2v, and yosys compatibility
2021-09-27 08:55:10 -04:00
Blaise Tine
9b04f3d9d6
Updated README and synthesis scripts
2021-09-22 07:50:47 -07:00
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a46c32ed4b
Adding Vortex Yosys build support
2021-09-08 23:04:33 -04:00
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fe5112b6c1
minor updates
2021-09-05 23:05:21 -07:00
Blaise Tine
33a83cc733
adding fpu_core synthesis build
2021-09-05 20:27:55 -07:00
Blaise Tine
26e94dde44
cache area optimization by disabling BRAM read-during-write bypassing for tag/data stores
2021-08-26 12:27:38 -07:00
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2a27bfbfd5
LKG Build (reset network update -fmax=236 mhz 4c)
2021-08-23 01:59:22 -07:00
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bb1ceffadd
rebase master update
2021-07-30 21:03:14 -07:00
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0319283ea7
minor update
2021-07-20 21:42:22 -07:00
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6b641ceb21
minor update
2021-07-17 15:26:04 -07:00
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ff5ec3adc8
minor update
2021-07-17 07:23:35 -07:00
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5c58f7eec6
minor update
2021-07-16 12:57:50 -07:00
Blaise Tine
5c40422e4f
dcache response bus optimization
2021-07-12 10:14:48 -07:00
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f84c8a0b5d
instr_sched => ibuffer
2021-06-27 19:36:43 -07:00
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1ea738ed26
lkg build
2021-06-25 16:28:10 -07:00
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57143f5889
synthesis optimizations
2021-06-17 16:43:43 -07:00
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03406c0a3f
project tests refactoring
2021-06-13 17:42:04 -07:00
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47c3234659
minor update
2021-06-13 10:58:48 -07:00
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3cc1190cd7
CSRs I/O refactoring
2021-06-11 03:08:07 -07:00
Blaise Tine
adf033b0aa
non-cacheable memory address critical paths optimizations
2021-06-10 12:47:18 -07:00
Blaise Tine
b14825c8b9
update fpga build settings
2021-06-04 20:45:56 -07:00
Blaise Tine
79638c89de
adding synthesis build for shared memory
2021-05-25 22:02:42 -07:00
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7095a46066
minor update
2021-05-18 11:15:36 -07:00
Blaise Tine
bde6a69ea0
adding support for multi-banks memory bus
2021-05-04 07:32:03 -07:00
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ba16e88eab
stress test update
2021-05-03 12:24:41 -07:00
Blaise Tine
d504adb236
afu mem controller refactoring
2021-05-01 08:39:52 -07:00
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95f057bc2e
fpga build refactoring
2021-04-29 06:17:28 -07:00
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0910f95616
code refactoring
2021-04-26 02:35:50 -07:00
Blaise Tine
8410c49f53
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
Blaise Tine
2f5ccdcf45
quartus synthesis build update
2021-04-19 21:29:39 -07:00
