162 lines
4.6 KiB
Verilog
162 lines
4.6 KiB
Verilog
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`include "../VX_define.v"
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module Vortex
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#(
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parameter CACHE_SIZE = 4096, // Bytes
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parameter CACHE_WAYS = 1,
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parameter CACHE_BLOCK = 128, // Bytes
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parameter CACHE_BANKS = 8,
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localparam NUMBER_BANKS = 8,
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localparam NUM_WORDS_PER_BLOCK = 4
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)
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(
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input wire clk,
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input wire reset,
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input wire[31:0] icache_response_instruction,
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output wire[31:0] icache_request_pc_address,
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// IO
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output wire io_valid,
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output wire[31:0] io_data,
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// Req
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output reg [31:0] o_m_read_addr,
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output reg [31:0] o_m_evict_addr,
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output reg o_m_valid,
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output reg [31:0] o_m_writedata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
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output reg o_m_read_or_write,
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// Rsp
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input wire [31:0] i_m_readdata[NUMBER_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0],
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input wire i_m_ready,
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output wire out_ebreak
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);
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wire memory_delay;
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wire gpr_stage_delay;
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wire schedule_delay;
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// Dcache Interface
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VX_dcache_response_inter VX_dcache_rsp();
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VX_dcache_request_inter VX_dcache_req();
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wire temp_io_valid = (!memory_delay) && (|VX_dcache_req.out_cache_driver_in_valid) && (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) && (VX_dcache_req.out_cache_driver_in_address[0] == 32'h00010000);
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wire[31:0] temp_io_data = VX_dcache_req.out_cache_driver_in_data[0];
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assign io_valid = temp_io_valid;
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assign io_data = temp_io_data;
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VX_dram_req_rsp_inter VX_dram_req_rsp();
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assign o_m_read_addr = VX_dram_req_rsp.o_m_read_addr;
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assign o_m_evict_addr = VX_dram_req_rsp.o_m_evict_addr;
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assign o_m_valid = VX_dram_req_rsp.o_m_valid;
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assign o_m_read_or_write = VX_dram_req_rsp.o_m_read_or_write;
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assign VX_dram_req_rsp.i_m_ready = i_m_ready;
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genvar curr_bank;
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genvar curr_word;
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for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank = curr_bank + 1) begin
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for (curr_word = 0; curr_word < NUM_WORDS_PER_BLOCK; curr_word = curr_word + 1) begin
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assign o_m_writedata[curr_bank][curr_word] = VX_dram_req_rsp.o_m_writedata[curr_bank][curr_word];
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assign VX_dram_req_rsp.i_m_readdata[curr_bank][curr_word] = i_m_readdata[curr_bank][curr_word];
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end
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end
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// Icache Interface
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VX_icache_response_inter icache_response_fe();
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VX_icache_request_inter icache_request_fe();
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assign icache_response_fe.instruction = icache_response_instruction;
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assign icache_request_pc_address = icache_request_fe.pc_address;
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/////////////////////////////////////////////////////////////////////////
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// Front-end to Back-end
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VX_frE_to_bckE_req_inter VX_bckE_req(); // New instruction request to EXE/MEM
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// Back-end to Front-end
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VX_wb_inter VX_writeback_inter(); // Writeback to GPRs
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VX_branch_response_inter VX_branch_rsp(); // Branch Resolution to Fetch
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VX_jal_response_inter VX_jal_rsp(); // Jump resolution to Fetch
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// CSR Buses
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// VX_csr_write_request_inter VX_csr_w_req();
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VX_warp_ctl_inter VX_warp_ctl();
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VX_front_end vx_front_end(
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.clk (clk),
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.reset (reset),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.schedule_delay (schedule_delay),
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.icache_response_fe (icache_response_fe),
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.icache_request_fe (icache_request_fe),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.fetch_ebreak (out_ebreak)
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);
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VX_scheduler schedule(
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.clk (clk),
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.reset (reset),
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.memory_delay (memory_delay),
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.gpr_stage_delay (gpr_stage_delay),
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.VX_bckE_req (VX_bckE_req),
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.VX_writeback_inter(VX_writeback_inter),
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.schedule_delay (schedule_delay)
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);
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VX_back_end vx_back_end(
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.VX_warp_ctl (VX_warp_ctl),
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.VX_bckE_req (VX_bckE_req),
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.VX_jal_rsp (VX_jal_rsp),
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.VX_branch_rsp (VX_branch_rsp),
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.VX_dcache_rsp (VX_dcache_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_writeback_inter (VX_writeback_inter),
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.out_mem_delay (memory_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_dmem_controller VX_dmem_controller(
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.clk (clk),
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.reset (reset),
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.VX_dram_req_rsp(VX_dram_req_rsp),
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.VX_dcache_req (VX_dcache_req),
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.VX_dcache_rsp (VX_dcache_rsp)
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);
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// VX_csr_handler vx_csr_handler(
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// .clk (clk),
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// .in_decode_csr_address(decode_csr_address),
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// .VX_csr_w_req (VX_csr_w_req),
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// .in_wb_valid (VX_writeback_inter.wb_valid[0]),
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// .out_decode_csr_data (csr_decode_csr_data)
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// );
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endmodule // Vortex
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