469 lines
22 KiB
Verilog
469 lines
22 KiB
Verilog
`include "VX_cache_config.v"
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module VX_cache
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#(
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// Size of cache in bytes
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parameter CACHE_SIZE_BYTES = 1024,
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// Size of line inside a bank in bytes
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parameter BANK_LINE_SIZE_BYTES = 16,
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// Number of banks {1, 2, 4, 8,...}
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parameter NUMBER_BANKS = 8,
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// Size of a word in bytes
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parameter WORD_SIZE_BYTES = 16,
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// Number of Word requests per cycle {1, 2, 4, 8, ...}
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parameter NUMBER_REQUESTS = 2,
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// Number of cycles to complete stage 1 (read from memory)
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parameter STAGE_1_CYCLES = 2,
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// Function ID, {Dcache=0, Icache=1, Sharedmemory=2}
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parameter FUNC_ID = 3,
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// Queues feeding into banks Knobs {1, 2, 4, 8, ...}
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// Core Request Queue Size
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parameter REQQ_SIZE = 8,
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// Miss Reserv Queue Knob
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parameter MRVQ_SIZE = 8,
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// Dram Fill Rsp Queue Size
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parameter DFPQ_SIZE = 2,
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// Snoop Req Queue
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parameter SNRQ_SIZE = 8,
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// Queues for writebacks Knobs {1, 2, 4, 8, ...}
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// Core Writeback Queue Size
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parameter CWBQ_SIZE = 8,
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// Dram Writeback Queue Size
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parameter DWBQ_SIZE = 4,
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// Dram Fill Req Queue Size
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parameter DFQQ_SIZE = 8,
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// Lower Level Cache Hit Queue Size
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parameter LLVQ_SIZE = 16,
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// Fill Forward SNP Queue
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parameter FFSQ_SIZE = 8,
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// Fill Invalidator Size {Fill invalidator must be active}
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parameter FILL_INVALIDAOR_SIZE = 16,
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// Prefetcher
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parameter PRFQ_SIZE = 64,
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parameter PRFQ_STRIDE = 0,
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// Dram knobs
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parameter SIMULATED_DRAM_LATENCY_CYCLES = 10
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)
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(
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input wire clk,
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input wire reset,
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// Req Info
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input wire [NUMBER_REQUESTS-1:0] core_req_valid,
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input wire [NUMBER_REQUESTS-1:0][31:0] core_req_addr,
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input wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_req_writedata,
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input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_read,
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input wire[NUMBER_REQUESTS-1:0][2:0] core_req_mem_write,
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// Req meta
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input wire [4:0] core_req_rd,
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input wire [NUMBER_REQUESTS-1:0][1:0] core_req_wb,
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input wire [`NW_M1:0] core_req_warp_num,
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input wire [31:0] core_req_pc,
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output wire delay_req,
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// Core Writeback
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input wire core_no_wb_slot,
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output wire [NUMBER_REQUESTS-1:0] core_wb_valid,
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num,
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output wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] core_wb_readdata,
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output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_pc,
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output wire [NUMBER_REQUESTS-1:0][31:0] core_wb_address,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_rsp_addr,
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input wire [`IBANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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output wire dram_fill_accept,
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// Dram request
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output wire dram_req,
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output wire dram_req_write,
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output wire dram_req_read,
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output wire [31:0] dram_req_addr,
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output wire [31:0] dram_req_size,
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output wire [`IBANK_LINE_SIZE_RNG][31:0] dram_req_data,
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output wire dram_req_because_of_wb,
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input wire dram_req_delay,
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output wire dram_snp_full,
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// Snoop Req
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input wire snp_req,
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input wire[31:0] snp_req_addr,
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output wire snp_req_delay,
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// Snoop Forward
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output wire snp_fwd,
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output wire[31:0] snp_fwd_addr,
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input wire snp_fwd_delay
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);
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wire [NUMBER_BANKS-1:0][NUMBER_REQUESTS-1:0] per_bank_valids;
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wire [NUMBER_BANKS-1:0] per_bank_wb_pop;
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wire [NUMBER_BANKS-1:0] per_bank_wb_valid;
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wire [NUMBER_BANKS-1:0][`vx_clog2(NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
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wire [NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
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wire [NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
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wire [NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
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wire [NUMBER_BANKS-1:0][`WORD_SIZE_RNG] per_bank_wb_data;
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wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_pc;
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wire [NUMBER_BANKS-1:0][31:0] per_bank_wb_address;
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wire dfqq_full;
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wire[NUMBER_BANKS-1:0] per_bank_dram_fill_req;
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wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
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wire[NUMBER_BANKS-1:0] per_bank_dram_fill_accept;
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wire[NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire[NUMBER_BANKS-1:0] per_bank_dram_wb_req;
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wire[NUMBER_BANKS-1:0] per_bank_dram_because_of_snp;
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wire[NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
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wire[NUMBER_BANKS-1:0][`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] per_bank_dram_wb_req_data;
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wire[NUMBER_BANKS-1:0] per_bank_reqq_full;
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wire[NUMBER_BANKS-1:0] per_bank_snrq_full;
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wire[NUMBER_BANKS-1:0] per_bank_snp_fwd;
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wire[NUMBER_BANKS-1:0][31:0] per_bank_snp_fwd_addr;
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wire[NUMBER_BANKS-1:0] per_bank_snp_fwd_pop;
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assign delay_req = (|per_bank_reqq_full);
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assign snp_req_delay = (|per_bank_snrq_full);
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// assign dram_fill_accept = (NUMBER_BANKS == 1) ? per_bank_dram_fill_accept[0] : per_bank_dram_fill_accept[dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG]];
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assign dram_fill_accept = (|per_bank_dram_fill_accept);
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VX_cache_dram_req_arb #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (NUMBER_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUMBER_REQUESTS (NUMBER_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.PRFQ_SIZE (PRFQ_SIZE),
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.PRFQ_STRIDE (PRFQ_STRIDE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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)
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VX_cache_dram_req_arb
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(
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.clk (clk),
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.reset (reset),
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.dfqq_full (dfqq_full),
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.per_bank_dram_fill_req (per_bank_dram_fill_req),
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.per_bank_dram_fill_req_addr(per_bank_dram_fill_req_addr),
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.per_bank_dram_wb_queue_pop (per_bank_dram_wb_queue_pop),
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.per_bank_dram_wb_req (per_bank_dram_wb_req),
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.per_bank_dram_because_of_snp(per_bank_dram_because_of_snp),
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.per_bank_dram_wb_req_addr (per_bank_dram_wb_req_addr),
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.per_bank_dram_wb_req_data (per_bank_dram_wb_req_data),
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.dram_req (dram_req),
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.dram_req_write (dram_req_write),
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.dram_req_read (dram_req_read),
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.dram_req_addr (dram_req_addr),
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.dram_req_size (dram_req_size),
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.dram_req_data (dram_req_data),
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.dram_req_because_of_wb (dram_req_because_of_wb),
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.dram_req_delay (dram_req_delay)
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);
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VX_cache_core_req_bank_sel #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (NUMBER_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUMBER_REQUESTS (NUMBER_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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)
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VX_cache_core_req_bank_sell
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(
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.core_req_valid (core_req_valid),
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.core_req_addr (core_req_addr),
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.per_bank_valids(per_bank_valids)
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);
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VX_cache_wb_sel_merge #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (NUMBER_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
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.NUMBER_REQUESTS (NUMBER_REQUESTS),
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.STAGE_1_CYCLES (STAGE_1_CYCLES),
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.FUNC_ID (FUNC_ID),
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.REQQ_SIZE (REQQ_SIZE),
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.MRVQ_SIZE (MRVQ_SIZE),
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.DFPQ_SIZE (DFPQ_SIZE),
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.SNRQ_SIZE (SNRQ_SIZE),
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.CWBQ_SIZE (CWBQ_SIZE),
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.DWBQ_SIZE (DWBQ_SIZE),
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.DFQQ_SIZE (DFQQ_SIZE),
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.LLVQ_SIZE (LLVQ_SIZE),
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.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
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.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
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)
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VX_cache_core_wb_sel_merge
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(
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.per_bank_wb_valid (per_bank_wb_valid),
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.per_bank_wb_tid (per_bank_wb_tid),
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.per_bank_wb_rd (per_bank_wb_rd),
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.per_bank_wb_pc (per_bank_wb_pc),
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.per_bank_wb_wb (per_bank_wb_wb),
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.per_bank_wb_warp_num(per_bank_wb_warp_num),
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.per_bank_wb_data (per_bank_wb_data),
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.per_bank_wb_pop (per_bank_wb_pop),
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.per_bank_wb_address (per_bank_wb_address),
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.core_no_wb_slot (core_no_wb_slot),
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.core_wb_valid (core_wb_valid),
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.core_wb_req_rd (core_wb_req_rd),
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.core_wb_req_wb (core_wb_req_wb),
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.core_wb_warp_num (core_wb_warp_num),
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.core_wb_readdata (core_wb_readdata),
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.core_wb_address (core_wb_address),
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.core_wb_pc (core_wb_pc)
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);
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// Snoop Forward Logic
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VX_snp_fwd_arb #(.NUMBER_BANKS(NUMBER_BANKS)) VX_snp_fwd_arb(
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.per_bank_snp_fwd (per_bank_snp_fwd),
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.per_bank_snp_fwd_addr(per_bank_snp_fwd_addr),
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.per_bank_snp_fwd_pop (per_bank_snp_fwd_pop),
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.snp_fwd (snp_fwd),
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.snp_fwd_addr (snp_fwd_addr),
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.snp_fwd_delay (snp_fwd_delay)
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);
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// Snoop Forward Logic
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genvar curr_bank;
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generate
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for (curr_bank = 0; curr_bank < NUMBER_BANKS; curr_bank=curr_bank+1) begin
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wire [NUMBER_REQUESTS-1:0] curr_bank_valids;
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wire [NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
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wire [NUMBER_REQUESTS-1:0][`WORD_SIZE_RNG] curr_bank_writedata;
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wire [4:0] curr_bank_rd;
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wire [NUMBER_REQUESTS-1:0][1:0] curr_bank_wb;
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wire [`NW_M1:0] curr_bank_warp_num;
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wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_read;
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wire [NUMBER_REQUESTS-1:0][2:0] curr_bank_mem_write;
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wire [31:0] curr_bank_pc;
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wire curr_bank_wb_pop;
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wire curr_bank_wb_valid;
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wire [`vx_clog2(NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
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wire [31:0] curr_bank_wb_pc;
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wire [4:0] curr_bank_wb_rd;
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wire [1:0] curr_bank_wb_wb;
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wire [`NW_M1:0] curr_bank_wb_warp_num;
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wire [`WORD_SIZE_RNG] curr_bank_wb_data;
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wire [31:0] curr_bank_wb_address;
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wire curr_bank_dram_fill_rsp;
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wire [31:0] curr_bank_dram_fill_rsp_addr;
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wire [`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_fill_rsp_data;
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wire curr_bank_dram_fill_accept;
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wire curr_bank_dfqq_full;
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wire curr_bank_dram_fill_req;
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wire curr_bank_dram_because_of_snp;
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wire curr_bank_dram_snp_full;
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wire[31:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_wb_queue_pop;
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wire curr_bank_dram_wb_req;
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wire[31:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_SIZE_RNG][`WORD_SIZE-1:0] curr_bank_dram_wb_req_data;
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wire curr_bank_snp_req;
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wire[31:0] curr_bank_snp_req_addr;
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wire curr_bank_reqq_full;
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wire curr_bank_snp_fwd;
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wire[31:0] curr_bank_snp_fwd_addr;
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wire curr_bank_snp_fwd_pop;
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wire curr_bank_snrq_full;
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// Core Req
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assign curr_bank_valids = per_bank_valids[curr_bank];
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assign curr_bank_addr = core_req_addr;
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assign curr_bank_writedata = core_req_writedata;
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assign curr_bank_rd = core_req_rd;
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assign curr_bank_wb = core_req_wb;
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assign curr_bank_pc = core_req_pc;
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assign curr_bank_warp_num = core_req_warp_num;
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assign curr_bank_mem_read = core_req_mem_read;
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assign curr_bank_mem_write = core_req_mem_write;
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assign per_bank_reqq_full[curr_bank] = curr_bank_reqq_full;
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// Core WB
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assign curr_bank_wb_pop = per_bank_wb_pop[curr_bank];
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assign per_bank_wb_valid [curr_bank] = curr_bank_wb_valid;
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assign per_bank_wb_tid [curr_bank] = curr_bank_wb_tid;
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assign per_bank_wb_rd [curr_bank] = curr_bank_wb_rd;
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assign per_bank_wb_wb [curr_bank] = curr_bank_wb_wb;
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assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
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assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
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assign per_bank_wb_pc [curr_bank] = curr_bank_wb_pc;
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assign per_bank_wb_address [curr_bank] = curr_bank_wb_address;
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// Dram fill request
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assign curr_bank_dfqq_full = dfqq_full;
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assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
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assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
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// Dram fill response
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assign curr_bank_dram_fill_rsp = (NUMBER_BANKS == 1) || (dram_fill_rsp && (curr_bank_dram_fill_rsp_addr[`BANK_SELECT_ADDR_RNG] == curr_bank));
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assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
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assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
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assign per_bank_dram_fill_accept[curr_bank] = curr_bank_dram_fill_accept;
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// Dram writeback request
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assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
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assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
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assign per_bank_dram_because_of_snp[curr_bank] = curr_bank_dram_because_of_snp;
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assign per_bank_dram_wb_req_addr[curr_bank] = curr_bank_dram_wb_req_addr;
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assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
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// Snoop Request
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assign curr_bank_snp_req = snp_req && (snp_req_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
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assign curr_bank_snp_req_addr = snp_req_addr;
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assign per_bank_snrq_full[curr_bank] = curr_bank_snrq_full;
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// Snoop Fwd
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assign curr_bank_snp_fwd_pop = per_bank_snp_fwd_pop[curr_bank];
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assign per_bank_snp_fwd[curr_bank] = curr_bank_snp_fwd;
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assign per_bank_snp_fwd_addr[curr_bank] = curr_bank_snp_fwd_addr;
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VX_bank #(
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.CACHE_SIZE_BYTES (CACHE_SIZE_BYTES),
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.BANK_LINE_SIZE_BYTES (BANK_LINE_SIZE_BYTES),
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.NUMBER_BANKS (NUMBER_BANKS),
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.WORD_SIZE_BYTES (WORD_SIZE_BYTES),
|
|
.NUMBER_REQUESTS (NUMBER_REQUESTS),
|
|
.STAGE_1_CYCLES (STAGE_1_CYCLES),
|
|
.FUNC_ID (FUNC_ID),
|
|
.REQQ_SIZE (REQQ_SIZE),
|
|
.MRVQ_SIZE (MRVQ_SIZE),
|
|
.DFPQ_SIZE (DFPQ_SIZE),
|
|
.SNRQ_SIZE (SNRQ_SIZE),
|
|
.CWBQ_SIZE (CWBQ_SIZE),
|
|
.DWBQ_SIZE (DWBQ_SIZE),
|
|
.DFQQ_SIZE (DFQQ_SIZE),
|
|
.LLVQ_SIZE (LLVQ_SIZE),
|
|
.FFSQ_SIZE (FFSQ_SIZE),
|
|
.FILL_INVALIDAOR_SIZE (FILL_INVALIDAOR_SIZE),
|
|
.SIMULATED_DRAM_LATENCY_CYCLES(SIMULATED_DRAM_LATENCY_CYCLES)
|
|
)
|
|
bank
|
|
(
|
|
.clk (clk),
|
|
.reset (reset),
|
|
// Core req
|
|
.delay_req (delay_req),
|
|
.bank_valids (curr_bank_valids),
|
|
.bank_addr (curr_bank_addr),
|
|
.bank_writedata (curr_bank_writedata),
|
|
.bank_rd (curr_bank_rd),
|
|
.bank_wb (curr_bank_wb),
|
|
.bank_pc (curr_bank_pc),
|
|
.bank_warp_num (curr_bank_warp_num),
|
|
.bank_mem_read (curr_bank_mem_read),
|
|
.bank_mem_write (curr_bank_mem_write),
|
|
.reqq_full (curr_bank_reqq_full),
|
|
|
|
// Output core wb
|
|
.bank_wb_pop (curr_bank_wb_pop),
|
|
.bank_wb_valid (curr_bank_wb_valid),
|
|
.bank_wb_tid (curr_bank_wb_tid),
|
|
.bank_wb_rd (curr_bank_wb_rd),
|
|
.bank_wb_wb (curr_bank_wb_wb),
|
|
.bank_wb_warp_num (curr_bank_wb_warp_num),
|
|
.bank_wb_data (curr_bank_wb_data),
|
|
.bank_wb_pc (curr_bank_wb_pc),
|
|
.bank_wb_address (curr_bank_wb_address),
|
|
|
|
// Dram fill req
|
|
.dram_fill_req (curr_bank_dram_fill_req),
|
|
.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
|
|
.dram_fill_req_queue_full(curr_bank_dfqq_full),
|
|
|
|
// Dram fill rsp
|
|
.dram_fill_rsp (curr_bank_dram_fill_rsp),
|
|
.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
|
|
.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
|
|
.dram_fill_accept (curr_bank_dram_fill_accept),
|
|
|
|
// Dram writeback
|
|
.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
|
|
.dram_wb_req (curr_bank_dram_wb_req),
|
|
.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
|
|
.dram_wb_req_data (curr_bank_dram_wb_req_data),
|
|
.dram_because_of_snp (curr_bank_dram_because_of_snp),
|
|
.dram_snp_full (curr_bank_dram_snp_full),
|
|
|
|
// Snoop Request
|
|
.snp_req (curr_bank_snp_req),
|
|
.snp_req_addr (curr_bank_snp_req_addr),
|
|
.snrq_full (curr_bank_snrq_full),
|
|
|
|
// Snoop Fwd
|
|
.snp_fwd (curr_bank_snp_fwd),
|
|
.snp_fwd_addr (curr_bank_snp_fwd_addr),
|
|
.snp_fwd_pop (curr_bank_snp_fwd_pop)
|
|
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
|
|
endmodule |