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project directories restructuring

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This commit is contained in:
Blaise Tine
2020-04-14 08:24:49 -04:00
parent fc155e1223
commit 3bbaea1332
46 changed files with 0 additions and 5199 deletions
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0
hw/rtl/Makefile → hw/Makefile
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124
hw/old_rtl/modelsim/Makefile
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ALL:sim
#TOOL INPUT
SRC = \
vortex_dpi.cpp \
vortex_tb.v \
../VX_define.v \
../VX_define_synth.v \
../interfaces/VX_branch_response_inter.v \
../interfaces/VX_csr_req_inter.v \
../interfaces/VX_csr_wb_inter.v \
../interfaces/VX_dcache_request_inter.v \
../interfaces/VX_dcache_response_inter.v \
../interfaces/VX_dram_req_rsp_inter.v \
../interfaces/VX_exec_unit_req_inter.v \
../interfaces/VX_frE_to_bckE_req_inter.v \
../interfaces/VX_gpr_clone_inter.v \
../interfaces/VX_gpr_data_inter.v \
../interfaces/VX_gpr_jal_inter.v \
../interfaces/VX_gpr_read_inter.v \
../interfaces/VX_gpr_wspawn_inter.v \
../interfaces/VX_gpu_inst_req_inter.v \
../interfaces/VX_icache_request_inter.v \
../interfaces/VX_icache_response_inter.v \
../interfaces/VX_inst_exec_wb_inter.v \
../interfaces/VX_inst_mem_wb_inter.v \
../interfaces/VX_inst_meta_inter.v \
../interfaces/VX_jal_response_inter.v \
../interfaces/VX_join_inter.v \
../interfaces/VX_lsu_req_inter.v \
../interfaces/VX_mem_req_inter.v \
../interfaces/VX_mw_wb_inter.v \
../interfaces/VX_warp_ctl_inter.v \
../interfaces/VX_wb_inter.v \
../interfaces/VX_wstall_inter.v \
../VX_alu.v \
../VX_back_end.v \
../VX_csr_handler.v \
../VX_csr_wrapper.v \
../VX_decode.v \
../VX_dmem_controller.v \
../VX_execute_unit.v \
../VX_fetch.v \
../VX_front_end.v \
../VX_generic_priority_encoder.v \
../VX_generic_register.v \
../VX_generic_stack.v \
../VX_gpgpu_inst.v \
../VX_gpr.v \
../VX_gpr_stage.v \
../VX_gpr_wrapper.v \
../VX_inst_multiplex.v \
../VX_lsu.v \
../VX_lsu_addr_gen.v \
../VX_priority_encoder.v \
../VX_priority_encoder_w_mask.v \
../VX_scheduler.v \
../VX_warp.v \
../VX_countones.v \
../VX_warp_scheduler.v \
../VX_writeback.v \
../Vortex.v \
../byte_enabled_simple_dual_port_ram.v \
../cache/VX_Cache_Bank.v \
../cache/VX_cache_bank_valid.v \
../cache/VX_cache_data.v \
../cache/VX_d_cache.v \
../cache/VX_generic_pe.v \
../cache/cache_set.v \
../cache/VX_cache_data_per_index.v \
../pipe_regs/VX_d_e_reg.v \
../pipe_regs/VX_f_d_reg.v \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v \
../../models/memory/cln28hpm/rf2_32x19_wm0/rf2_32x19_wm0.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "VoptFlow = 0; \
vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"
OPT=-sv -sv12compat
LIB = vortex_lib
# LOG=-logfile vortex_tb.log
LOG=
# setup: source cshrc.modelsim
# vlib
lib:
vlib vortex_lib
comp:
vlog $(OPT) -work $(LIB) $(SRC)
# vlog -O0 -dpiheader vortex_dpi.h $(OPT) -work $(LIB) $(SRC)
sim: comp
# vsim vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log
vsim -novopt vortex_tb $(LOG) -c -lib $(LIB) $(CMD) > vortex_sim.log

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hw/old_rtl/modelsim/cshrc.modelsim
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setenv PATH "${PATH}:/tools/mentor/modelsim/ms106a/modeltech/bin"
setenv MTI_VCO_MODE 1
if (${?LM_LICENSE_FILE}) then
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu:${LM_LICENSE_FILE}"
else
setenv LM_LICENSE_FILE "1717@ece-linlic.ece.gatech.edu"
endif
setenv MGLS_LICENSE_FILE 1717@ece-linlic.ece.gatech.edu

2275
hw/old_rtl/modelsim/modelsim.mpf
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328
hw/old_rtl/modelsim/vortex_dpi.cpp
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// #include <iostream>
// #include "VX_define.h"
#include <../simulate/ram.h>
#include <stdio.h>
#include <math.h>
#include "svdpi.h"
#include "../simulate/VX_define.h"
// #include "vortex_dpi.h"
extern "C" {
void load_file (char * filename);
void ibus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void dbus_driver (bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit(int);
}
RAM ram;
bool refill;
unsigned refill_addr;
bool i_refill;
unsigned i_refill_addr;
unsigned num_cycles;
unsigned getIndex(int, int, int);
unsigned calculate_bits_per_bank_num(int);
unsigned getIndex(int r, int c, int numCols)
{
return (r * numCols) + c;
}
unsigned calculate_bits_per_bank_num(int num)
{
int shifted_num = 0;
for(int i = 0; i < num; i++){
shifted_num = (shifted_num << 1)| 1 ;
}
return shifted_num;
}
void load_file(char * filename)
{
num_cycles = 0;
// printf("\n\n\n\n**********************\n");
// printf("Inside load_file\n");
fprintf(stderr, "\n\n\n\n**********************\n");
loadHexImpl(filename, &ram);
// printf("Filename: %s\n", filename);
refill = false;
i_refill = false;
}
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (i_refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
i_refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = i_refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
i_refill = true;
i_refill_addr = o_m_read_addr;
}
}
}
}
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready)
{
// Default values
{
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
(*i_m_ready) = false;
for (int i = 0; i < cache_banks; i++)
{
for (int j = 0; j < num_words_per_block; j++)
{
unsigned index = getIndex(i,j, num_words_per_block);
real_i_m_readdata[index].aval = 0x506070;
// svGetArrElemPtr2(i_m_readdata, i, j);
// svPutLogicArrElem2VecVal(i_m_readdata, i, j);
// i_m_readdata[getIndex(i,j, num_words_per_block)] = 0;
}
}
}
if (clk)
{
// Do nothing on positive edge
}
else
{
if (refill)
{
// svGetArrElemPtr2((*i_m_readdata), 0,0);
// fprintf(stderr, "--------------------------------\n");
refill = false;
*i_m_ready = true;
s_vpi_vecval * real_i_m_readdata = (s_vpi_vecval *) i_m_readdata;
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = refill_addr + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
unsigned value;
ram.getWord(new_addr, &value);
fprintf(stdout, "-------- (%x) i_m_readdata[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, value);
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
// fprintf(stderr, "Index: %d (%d, %d) = %x\n", index, bank_num, offset_num, value);
real_i_m_readdata[index].aval = value;
}
}
else
{
if (o_m_valid)
{
s_vpi_vecval * real_o_m_writedata = (s_vpi_vecval *) o_m_writedata;
if (o_m_read_or_write)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
for (int curr_e = 0; curr_e < (cache_banks*num_words_per_block); curr_e++)
{
unsigned new_addr = (o_m_evict_addr) + (4*curr_e);
unsigned addr_without_byte = new_addr >> 2;
unsigned bits_per_bank = (int)log2(cache_banks);
// unsigned maskbits_per_bank = calculate_bits_per_bank_num(bits_per_bank);
unsigned maskbits_per_bank = cache_banks - 1;
unsigned bank_num = addr_without_byte & maskbits_per_bank;
unsigned addr_wihtout_bank = addr_without_byte >> bits_per_bank;
unsigned offset_num = addr_wihtout_bank & (num_words_per_block-1);
// unsigned offset_num = addr_wihtout_bank & 0x3;
unsigned index = getIndex(bank_num,offset_num, num_words_per_block);
unsigned new_value = real_o_m_writedata[index].aval;
// new_value = (unsigned *) svGetArrElemPtr2(o_m_writedata, bank_num, offset_num);
// new_value = getElem(o_m_writedata, index);
// unsigned new_value = o_m_writedata[getIndex(bank_num,offset_num, num_words_per_block)];
ram.writeWord( new_addr, &new_value);
fprintf(stdout, "+++++++ (%x) writeback[%d][%d] (%d) = %x\n", new_addr, bank_num, offset_num, curr_e, new_value);
}
}
// Respond next cycle
refill = true;
refill_addr = o_m_read_addr;
}
}
}
}
void io_handler(bool clk, bool io_valid, unsigned io_data)
{
// printf("Inside io_handler\n");
if (clk)
{
// Do nothing
}
else
{
if (io_valid)
{
uint32_t data_write = (uint32_t) (io_data);
fprintf(stderr, "%c", (char) data_write);
fflush(stderr);
}
}
}
void gracefulExit(int cycles)
{
fprintf(stderr, "*********************\n\n");
fprintf(stderr, "DPI Cycle Num: %d\tVerilog Cycle Num: %d\n", num_cycles, cycles);
}

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hw/old_rtl/modelsim/vortex_dpi.h
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extern "C" {
void load_file (char * filename);
void dbus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void ibus_driver(bool clk, unsigned o_m_read_addr, unsigned o_m_evict_addr, bool o_m_valid, svLogicVecVal * o_m_writedata, bool o_m_read_or_write, unsigned cache_banks, unsigned num_words_per_block, svLogicVecVal * i_m_readdata, bool * i_m_ready);
void io_handler (bool clk, bool io_valid, unsigned io_data);
void gracefulExit();
}

160
hw/old_rtl/modelsim/vortex_tb.v
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`include "../VX_define.v"
//`define NUMBER_BANKS 8
//`define NUM_WORDS_PER_BLOCK 4
`define ARM_UD_MODEL
`timescale 1ns/1ps
import "DPI-C" load_file = function void load_file(input string filename);
/*
import "DPI-C" ibus_driver = function void ibus_driver(input logic clk, input int pc_addr,
output int instruction);
*/
import "DPI-C" ibus_driver = function void ibus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" dbus_driver = function void dbus_driver( input logic clk,
input int o_m_read_addr,
input int o_m_evict_addr,
input logic o_m_valid,
input reg[31:0] o_m_writedata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
input logic o_m_read_or_write,
input int cache_banks,
input int words_per_block,
// Rsp
output reg[31:0] i_m_readdata[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0],
output logic i_m_ready);
import "DPI-C" io_handler = function void io_handler(input logic clk, input logic io_valid, input int io_data);
import "DPI-C" gracefulExit = function void gracefulExit(input int cycle_num);
module vortex_tb (
);
int cycle_num;
reg clk;
reg reset;
reg[31:0] icache_response_instruction;
reg[31:0] icache_request_pc_address;
// IO
reg io_valid;
reg[31:0] io_data;
// Req
reg [31:0] o_m_read_addr_d;
reg [31:0] o_m_evict_addr_d;
reg o_m_valid_d;
reg [31:0] o_m_writedata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_d;
// Rsp
reg [31:0] i_m_readdata_d[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_d;
// Req
reg [31:0] o_m_read_addr_i;
reg [31:0] o_m_evict_addr_i;
reg o_m_valid_i;
reg [31:0] o_m_writedata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg o_m_read_or_write_i;
// Rsp
reg [31:0] i_m_readdata_i[`ICACHE_BANKS - 1:0][`ICACHE_NUM_WORDS_PER_BLOCK-1:0];
reg i_m_ready_i;
reg out_ebreak;
reg[31:0] hi;
integer temp;
initial begin
// $fdumpfile("vortex1.vcd");
load_file("../../runtime/mains/simple/vx_simple_main.hex");
// load_file("../../emulator/riscv_tests/rv32ui-p-add.hex");
//load_file("../../kernel/vortex_test.hex");
$dumpvars(0, vortex_tb);
reset = 1;
clk = 0;
#5 reset = 1;
clk = 1;
cycle_num = 0;
end
Vortex vortex(
.clk (clk),
.reset (reset),
.icache_response_instruction (icache_response_instruction),
.icache_request_pc_address (icache_request_pc_address),
.io_valid (io_valid),
.io_data (io_data),
.o_m_read_addr_d (o_m_read_addr_d),
.o_m_evict_addr_d (o_m_evict_addr_d),
.o_m_valid_d (o_m_valid_d),
.o_m_writedata_d (o_m_writedata_d),
.o_m_read_or_write_d (o_m_read_or_write_d),
.i_m_readdata_d (i_m_readdata_d),
.i_m_ready_d (i_m_ready_d),
.o_m_read_addr_i (o_m_read_addr_i),
.o_m_evict_addr_i (o_m_evict_addr_i),
.o_m_valid_i (o_m_valid_i),
.o_m_writedata_i (o_m_writedata_i),
.o_m_read_or_write_i (o_m_read_or_write_i),
.i_m_readdata_i (i_m_readdata_i),
.i_m_ready_i (i_m_ready_i),
.out_ebreak (out_ebreak)
);
always @(negedge clk) begin
ibus_driver(clk, o_m_read_addr_i, o_m_evict_addr_i, o_m_valid_i, o_m_writedata_i, o_m_read_or_write_i, `ICACHE_BANKS, `ICACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_i, i_m_ready_i);
dbus_driver(clk, o_m_read_addr_d, o_m_evict_addr_d, o_m_valid_d, o_m_writedata_d, o_m_read_or_write_d, `DCACHE_BANKS, `DCACHE_NUM_WORDS_PER_BLOCK, i_m_readdata_d, i_m_ready_d);
io_handler (clk, io_valid, io_data);
end
always @(posedge clk) begin
if (out_ebreak) begin
gracefulExit(cycle_num);
#40 $finish;
end
end
always @(posedge clk) begin
cycle_num = cycle_num + 1;
end
always @(clk, posedge reset) begin
if (reset) begin
reset = 0;
clk = 0;
end
#5 clk <= ~clk;
end
endmodule

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hw/old_rtl/modelsim/work/_vmake
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m255
K4
z0
cModel Technology

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hw/old_rtl/quartus/Makefile
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PROJECT = Vortex
TOP_LEVEL_ENTITY = Vortex
SRC_FILE = Vortex.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N4F45I3SG
# Executable Configuration
SYN_ARGS = --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: smart.log $(PROJECT).asm.rpt $(PROJECT).sta.rpt
syn: smart.log $(PROJECT).syn.rpt
fit: smart.log $(PROJECT).fit.rpt
asm: smart.log $(PROJECT).asm.rpt
sta: smart.log $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: syn.chg $(SOURCE_FILES)
/tools/reconfig/intel/18.0/quartus/bin/quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: fit.chg $(PROJECT).syn.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: asm.chg $(PROJECT).fit.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: sta.chg $(PROJECT).fit.rpt
/tools/reconfig/intel/18.0/quartus/bin/quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
/tools/reconfig/intel/18.0/quartus/bin/quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "P;$(PROJECT).sof"
clean:
rm -rf *.rpt *.chg *.qsf *.qpf smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db output_files tmp-clearbox

30
hw/old_rtl/quartus/VX_gpr_syn.qpf
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@@ -1,30 +0,0 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
# Date created = 00:18:19 September 11, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "18.0"
DATE = "00:18:19 September 11, 2019"
# Revisions
PROJECT_REVISION = "VX_gpr_syn"

63
hw/old_rtl/quartus/VX_gpr_syn.qsf
View File

@@ -1,63 +0,0 @@
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:18:19 SEPTEMBER 11, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Pro Edition"
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115N4F45I3SG
set_global_assignment -name TOP_LEVEL_ENTITY VX_gpr_syn
set_global_assignment -name SEARCH_PATH ../
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
set_global_assignment -name VERILOG_FILE ../VX_decode.v
set_global_assignment -name VERILOG_FILE ../VX_execute.v
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
set_global_assignment -name VERILOG_FILE ../VX_memory.v
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
set_global_assignment -name VERILOG_FILE ../VX_warp.v
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
set_global_assignment -name VERILOG_FILE ../Vortex.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL

1
hw/old_rtl/quartus/asm.chg
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@@ -1 +0,0 @@
done

1
hw/old_rtl/quartus/fit.chg
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@@ -1 +0,0 @@
done

1
hw/old_rtl/quartus/map.chg
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@@ -1 +0,0 @@
Wed Sep 11 00:18:22 2019

88
hw/old_rtl/quartus/project.tcl
View File

@@ -1,88 +0,0 @@
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name SEARCH_PATH ../
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
set_global_assignment -name VERILOG_FILE ../VX_alu.v
set_global_assignment -name VERILOG_FILE ../VX_back_end.v
set_global_assignment -name VERILOG_FILE ../VX_context.v
set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
set_global_assignment -name VERILOG_FILE ../VX_decode.v
set_global_assignment -name VERILOG_FILE ../VX_define.v
set_global_assignment -name VERILOG_FILE ../VX_execute.v
set_global_assignment -name VERILOG_FILE ../VX_fetch.v
set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
set_global_assignment -name VERILOG_FILE ../VX_front_end.v
set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
set_global_assignment -name VERILOG_FILE ../VX_memory.v
set_global_assignment -name VERILOG_FILE ../VX_register_file.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
set_global_assignment -name VERILOG_FILE ../VX_warp.v
set_global_assignment -name VERILOG_FILE ../VX_writeback.v
set_global_assignment -name VERILOG_FILE ../Vortex.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
project_close
# set_global_assignment -name VERILOG_FILE $opts(src)

27
hw/old_rtl/quartus/smart.log
View File

@@ -1,27 +0,0 @@
Info (292036): Thank you for using the Quartus Prime software 30-day evaluation. You have 0 days remaining (until Sep 11, 2019) to use the Quartus Prime software with compilation and simulation support.
Info: *******************************************************************
Info: Running Quartus Prime Shell
Info: Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and its AMPP partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details.
Info: Processing started: Wed Sep 11 00:18:22 2019
Info: Command: quartus_sh --determine_smart_action VX_gpr_syn
Info: Quartus(args): VX_gpr_syn
Info: SMART_ACTION = SOURCE
Info (23030): Evaluation of Tcl script /tools/reconfig/intel/18.0/quartus/common/tcl/internal/qsh_smart.tcl was successful
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 687 megabytes
Info: Processing ended: Wed Sep 11 00:18:22 2019
Info: Elapsed time: 00:00:00
Info: Total CPU time (on all processors): 00:00:00

1
hw/old_rtl/quartus/sta.chg
View File

@@ -1 +0,0 @@
done

1
hw/old_rtl/quartus/syn.chg
View File

@@ -1 +0,0 @@
done

40
hw/old_rtl/quartus/vortex.ini
View File

@@ -1,40 +0,0 @@
load_package flow
set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
set_global_assignment -name VERILOG_FILE ../VX_gpr.v
set_global_assignment -name SDC_FILE vortex.sdc
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 80
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
# pins configuration
package require cmdline
proc make_all_pins_virtual { args } {
set options {\
{ "exclude.arg" "" "List of signals to exclude" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
remove_all_instance_assignments -name VIRTUAL_PIN
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
if { -1 == [lsearch -exact $opts(excludes) $pin_name] } {
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
} else {
post_message "Skipping VIRTUAL_PIN assignment to $pin_name"
}
}
export_assignments
}
make_all_pins_virtual -exclude { clk, reset }

1
hw/old_rtl/quartus/vortex.sdc
View File

@@ -1 +0,0 @@
create_clock -name {clk} -period "400 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

100
hw/old_rtl/simulate/VX_define.h
View File

@@ -1,100 +0,0 @@
#define NT 4
#define NT_M1 (NT-1)
#define NW 8
#define CACHE_NUM_BANKS 8
#define CACHE_WORDS_PER_BLOCK 4
#define R_INST 51
#define L_INST 3
#define ALU_INST 19
#define S_INST 35
#define B_INST 99
#define LUI_INST 55
#define AUIPC_INST 23
#define JAL_INST 111
#define JALR_INST 103
#define SYS_INST 115
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
#define RS2_IMMED 1
#define RS2_REG 0
#define NO_MEM_READ 7
#define LB_MEM_READ 0
#define LH_MEM_READ 1
#define LW_MEM_READ 2
#define LBU_MEM_READ 4
#define LHU_MEM_READ 5
#define NO_MEM_WRITE 7
#define SB_MEM_WRITE 0
#define SH_MEM_WRITE 1
#define SW_MEM_WRITE 2
#define NO_BRANCH 0
#define BEQ 1
#define BNE 2
#define BLT 3
#define BGT 4
#define BLTU 5
#define BGTU 6
#define NO_ALU 15
#define ADD 0
#define SUB 1
#define SLLA 2
#define SLT 3
#define SLTU 4
#define XOR 5
#define SRL 6
#define SRA 7
#define OR 8
#define AND 9
#define SUBU 10
#define LUI_ALU 11
#define AUIPC_ALU 12
#define CSR_ALU_RW 13
#define CSR_ALU_RS 14
#define CSR_ALU_RC 15
// WRITEBACK
#define WB_ALU 1
#define WB_MEM 2
#define WB_JAL 3
#define NO_WB 0
// JAL
#define JUMP 1
#define NO_JUMP 0
// STALLS
#define STALL 1
#define NO_STALL 0
#define TAKEN 1
#define NOT_TAKEN 0
#define ZERO_REG 0
// COLORS
#define GREEN "\033[32m"
#define RED "\033[31m"
#define DEFAULT "\033[39m"

245
hw/old_rtl/simulate/ram.h
View File

@@ -1,245 +0,0 @@
#ifndef __RAM__
#define __RAM__
// #include "string.h"
#include <stdio.h>
#include <stdint.h>
// #include <cstdint>
// #define NULL 0
class RAM;
uint32_t hti(char);
uint32_t hToI(char *, uint32_t);
void loadHexImpl(char *,RAM*);
class RAM{
public:
uint8_t* mem[1 << 12];
RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
}
~RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
if(mem[i])
{
delete mem[i];
mem[i] = NULL;
}
}
}
uint8_t* get(uint32_t address){
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0x00;
ptr[i + 1] = 0x00;
ptr[i + 2] = 0x00;
ptr[i + 3] = 0x00;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
data[i] = (*this)[address + i];
}
}
void write(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
(*this)[address + i] = data[i];
}
}
void getBlock(uint32_t address, uint8_t *data)
{
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t * data)
{
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
// uint8_t hi = (uint8_t) *get(address + 0);
// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 1);
// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 2);
// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 3);
// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n";
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void writeWord(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t& operator [](uint32_t address) {
return *get(address);
}
};
// MEMORY UTILS
uint32_t hti(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
uint32_t hToI(char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti(c[i]) << ((size - i - 1) * 4);
}
return value;
}
void loadHexImpl(const char *path, RAM* mem) {
mem->clear();
FILE *fp = fopen(path, "r");
if(fp == 0){
printf("Path not found %s\n", path);
return;
// std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t*)mem->get(0))[1] = 0xf1401073;
((uint32_t*)mem->get(0))[2] = 0x30101073;
((uint32_t*)mem->get(0))[3] = 0x800000b7;
((uint32_t*)mem->get(0))[4] = 0x000080e7;
((uint32_t*)mem->get(0x80000000))[0] = 0x00000097;
((uint32_t*)mem->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t*)mem->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char* content = new char[size];
fread(content, 1, size, fp);
int offset = 0;
char* line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI(line + 1, 2);
uint32_t nextAddr = hToI(line + 3, 4) + offset;
uint32_t key = hToI(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(mem->get(add)) = hToI(line + 9 + i * 2, 2);
}
break;
case 2:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content) delete[] content;
}
#endif

1
hw/old_rtl/simulate/tb_debug.h
View File

@@ -1 +0,0 @@
#define VCD_OFF

105
hw/old_rtl/simulate/test_bench.cpp
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@@ -1,105 +0,0 @@
#include "test_bench.h"
#define NUM_TESTS 46
int main(int argc, char **argv)
{
// Verilated::debug(1);
Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(true);
#define ALL_TESTS
#ifdef ALL_TESTS
bool passed = true;
std::string tests[NUM_TESTS] = {
"../../emulator/riscv_tests/rv32ui-p-add.hex",
"../../emulator/riscv_tests/rv32ui-p-addi.hex",
"../../emulator/riscv_tests/rv32ui-p-and.hex",
"../../emulator/riscv_tests/rv32ui-p-andi.hex",
"../../emulator/riscv_tests/rv32ui-p-auipc.hex",
"../../emulator/riscv_tests/rv32ui-p-beq.hex",
"../../emulator/riscv_tests/rv32ui-p-bge.hex",
"../../emulator/riscv_tests/rv32ui-p-bgeu.hex",
"../../emulator/riscv_tests/rv32ui-p-blt.hex",
"../../emulator/riscv_tests/rv32ui-p-bltu.hex",
"../../emulator/riscv_tests/rv32ui-p-bne.hex",
"../../emulator/riscv_tests/rv32ui-p-jal.hex",
"../../emulator/riscv_tests/rv32ui-p-jalr.hex",
"../../emulator/riscv_tests/rv32ui-p-lb.hex",
"../../emulator/riscv_tests/rv32ui-p-lbu.hex",
"../../emulator/riscv_tests/rv32ui-p-lh.hex",
"../../emulator/riscv_tests/rv32ui-p-lhu.hex",
"../../emulator/riscv_tests/rv32ui-p-lui.hex",
"../../emulator/riscv_tests/rv32ui-p-lw.hex",
"../../emulator/riscv_tests/rv32ui-p-or.hex",
"../../emulator/riscv_tests/rv32ui-p-ori.hex",
"../../emulator/riscv_tests/rv32ui-p-sb.hex",
"../../emulator/riscv_tests/rv32ui-p-sh.hex",
"../../emulator/riscv_tests/rv32ui-p-simple.hex",
"../../emulator/riscv_tests/rv32ui-p-sll.hex",
"../../emulator/riscv_tests/rv32ui-p-slli.hex",
"../../emulator/riscv_tests/rv32ui-p-slt.hex",
"../../emulator/riscv_tests/rv32ui-p-slti.hex",
"../../emulator/riscv_tests/rv32ui-p-sltiu.hex",
"../../emulator/riscv_tests/rv32ui-p-sltu.hex",
"../../emulator/riscv_tests/rv32ui-p-sra.hex",
"../../emulator/riscv_tests/rv32ui-p-srai.hex",
"../../emulator/riscv_tests/rv32ui-p-srl.hex",
"../../emulator/riscv_tests/rv32ui-p-srli.hex",
"../../emulator/riscv_tests/rv32ui-p-sub.hex",
"../../emulator/riscv_tests/rv32ui-p-sw.hex",
"../../emulator/riscv_tests/rv32ui-p-xor.hex",
"../../emulator/riscv_tests/rv32ui-p-xori.hex",
"../../emulator/riscv_tests/rv32um-p-div.hex",
"../../emulator/riscv_tests/rv32um-p-divu.hex",
"../../emulator/riscv_tests/rv32um-p-mul.hex",
"../../emulator/riscv_tests/rv32um-p-mulh.hex",
"../../emulator/riscv_tests/rv32um-p-mulhsu.hex",
"../../emulator/riscv_tests/rv32um-p-mulhu.hex",
"../../emulator/riscv_tests/rv32um-p-rem.hex",
"../../emulator/riscv_tests/rv32um-p-remu.hex"
};
for (std::string s : tests) {
Vortex v;
std::cerr << s << std::endl;
bool curr = v.simulate(s);
if ( curr) std::cerr << GREEN << "Test Passed: " << s << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << s << std::endl;
passed = passed && curr;
}
if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n";
if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n";
return !passed;
#else
char testing[] = "../../emulator/riscv_tests/rv32ui-p-sw.hex";
Vortex v;
const char *testing;
if (argc >= 2) {
testing = argv[1];
} else {
testing = "../../kernel/vortex_test.hex";
}
std::cerr << testing << std::endl;
bool curr = v.simulate(testing);
if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl;
if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl;
return !curr;
#endif
}

433
hw/old_rtl/simulate/test_bench.h
View File

@@ -1,433 +0,0 @@
// C++ libraries
#include <utility>
#include <iostream>
#include <map>
#include <iterator>
#include <iomanip>
#include <fstream>
#include <unistd.h>
#include <vector>
#include <math.h>
#include <algorithm>
#include "VX_define.h"
#include "ram.h"
#include "VVortex.h"
#include "verilated.h"
#include "tb_debug.h"
#ifdef VCD_OUTPUT
#include <verilated_vcd_c.h>
#endif
unsigned long time_stamp = 0;
double sc_time_stamp()
{
return time_stamp / 1000.0;
}
class Vortex
{
public:
Vortex();
~Vortex();
bool simulate(std::string);
private:
void ProcessFile(void);
void print_stats(bool = true);
bool ibus_driver();
bool dbus_driver();
void io_handler();
RAM ram;
VVortex * vortex;
unsigned start_pc;
bool refill_d;
unsigned refill_addr_d;
bool refill_i;
unsigned refill_addr_i;
long int curr_cycle;
bool stop;
bool unit_test;
std::string instruction_file_name;
std::ofstream results;
int stats_static_inst;
int stats_dynamic_inst;
int stats_total_cycles;
int stats_fwd_stalls;
int stats_branch_stalls;
int debug_state;
int ibus_state;
int dbus_state;
int debug_return;
int debug_wait_num;
int debug_inst_num;
int debug_end_wait;
int debug_debugAddr;
double stats_sim_time;
#ifdef VCD_OUTPUT
VerilatedVcdC *m_trace;
#endif
};
Vortex::Vortex() : start_pc(0), curr_cycle(0), stop(true), unit_test(true), stats_static_inst(0), stats_dynamic_inst(-1),
stats_total_cycles(0), stats_fwd_stalls(0), stats_branch_stalls(0),
debug_state(0), ibus_state(0), dbus_state(0), debug_return(0),
debug_wait_num(0), debug_inst_num(0), debug_end_wait(0), debug_debugAddr(0)
{
this->vortex = new VVortex;
#ifdef VCD_OUTPUT
this->m_trace = new VerilatedVcdC;
this->vortex->trace(m_trace, 99);
this->m_trace->open("trace.vcd");
#endif
this->results.open("../results.txt");
}
Vortex::~Vortex()
{
#ifdef VCD_OUTPUT
m_trace->close();
#endif
this->results.close();
delete this->vortex;
}
void Vortex::ProcessFile(void)
{
loadHexImpl(this->instruction_file_name.c_str(), &this->ram);
}
void Vortex::print_stats(bool cycle_test)
{
if (cycle_test)
{
this->results << std::left;
// this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl;
this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl;
this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl;
this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
else
{
this->results << std::left;
this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl;
this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl;
}
uint32_t status;
ram.getWord(0, &status);
if (this->unit_test)
{
if (status == 1)
{
this->results << std::setw(24) << "# GRADE:" << "PASSING\n";
} else
{
this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n";
}
}
else
{
this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n";
}
this->stats_static_inst = 0;
this->stats_dynamic_inst = -1;
this->stats_total_cycles = 0;
this->stats_fwd_stalls = 0;
this->stats_branch_stalls = 0;
}
bool Vortex::ibus_driver()
{
vortex->i_m_ready_i = false;
{
// int dcache_num_words_per_block
if (refill_i)
{
refill_i = false;
vortex->i_m_ready_i = true;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
unsigned curr_addr = refill_addr_i + (4*curr_index);
unsigned curr_value;
ram.getWord(curr_addr, &curr_value);
vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value;
}
}
}
else
{
if (vortex->o_m_valid_i)
{
if (vortex->o_m_read_or_write_i)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
unsigned base_addr = vortex->o_m_evict_addr_i;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
unsigned curr_addr = base_addr + (4*curr_index);
unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word];
ram.writeWord( curr_addr, &curr_value);
}
}
}
// Respond next cycle
refill_i = true;
refill_addr_i = vortex->o_m_read_addr_i;
}
}
}
return false;
}
void Vortex::io_handler()
{
if (vortex->io_valid)
{
uint32_t data_write = (uint32_t) vortex->io_data;
char c = (char) data_write;
std::cerr << c;
// std::cout << c;
}
}
bool Vortex::dbus_driver()
{
vortex->i_m_ready_d = false;
{
// int dcache_num_words_per_block
if (refill_d)
{
refill_d = false;
vortex->i_m_ready_d = true;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
unsigned curr_addr = refill_addr_d + (4*curr_index);
unsigned curr_value;
ram.getWord(curr_addr, &curr_value);
vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value;
}
}
}
else
{
if (vortex->o_m_valid_d)
{
if (vortex->o_m_read_or_write_d)
{
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
unsigned base_addr = vortex->o_m_evict_addr_d;
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
{
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
{
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
unsigned curr_addr = base_addr + (4*curr_index);
unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word];
ram.writeWord( curr_addr, &curr_value);
}
}
}
// Respond next cycle
refill_d = true;
refill_addr_d = vortex->o_m_read_addr_d;
}
}
}
return false;
}
bool Vortex::simulate(std::string file_to_simulate)
{
this->instruction_file_name = file_to_simulate;
// this->results << "\n****************\t" << file_to_simulate << "\t****************\n";
this->ProcessFile();
// auto start_time = std::chrono::high_resolution_clock::now();
static bool stop = false;
static int counter = 0;
counter = 0;
stop = false;
// auto start_time = clock();
// vortex->reset = 1;
// vortex->reset = 0;
unsigned curr_inst;
unsigned new_PC;
// while (this->stop && (!(stop && (counter > 5))))
// {
// // std::cout << "************* Cycle: " << cycle << "\n";
// bool istop = ibus_driver();
// bool dstop = !dbus_driver();
// vortex->clk = 1;
// vortex->eval();
// vortex->clk = 0;
// vortex->eval();
// stop = istop && dstop;
// if (stop)
// {
// counter++;
// } else
// {
// counter = 0;
// }
// cycle++;
// }
bool istop;
bool dstop;
bool cont = false;
// for (int i = 0; i < 500; i++)
vortex->reset = 1;
vortex->clk = 0;
vortex->eval();
// m_trace->dump(10);
vortex->reset = 1;
vortex->clk = 1;
vortex->eval();
// m_trace->dump(11);
vortex->reset = 0;
vortex->clk = 0;
// unsigned cycles;
counter = 0;
this->stats_total_cycles = 12;
while (this->stop && ((counter < 5)))
// while (this->stats_total_cycles < 10)
{
// printf("-------------------------\n");
// std::cout << "Counter: " << counter << "\n";
// if ((this->stats_total_cycles) % 5000 == 0) std::cout << "************* Cycle: " << (this->stats_total_cycles) << "\n";
// dstop = !dbus_driver();
#ifdef VCD_OUTPUT
m_trace->dump(2*this->stats_total_cycles);
#endif
vortex->clk = 1;
vortex->eval();
istop = ibus_driver();
dstop = !dbus_driver();
io_handler();
#ifdef VCD_OUTPUT
m_trace->dump((2*this->stats_total_cycles)+1);
#endif
vortex->clk = 0;
vortex->eval();
// stop = istop && dstop;
stop = vortex->out_ebreak;
if (stop || cont)
// if (istop)
{
cont = true;
counter++;
} else
{
counter = 0;
}
++time_stamp;
++stats_total_cycles;
}
std::cerr << "New Total Cycles: " << (this->stats_total_cycles) << "\n";
int status = (unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb & 0xf;
// std::cout << "Last wb: " << std::hex << ((unsigned int) vortex->Vortex__DOT__vx_back_end__DOT__VX_wb__DOT__last_data_wb) << "\n";
// std::cout << "Something: " << result << '\n';
// uint32_t status;
// ram.getWord(0, &status);
this->print_stats();
return (status == 1);
// return (1 == 1);
}

0
hw/rtl/VX_cache/VX_bank.v → hw/rtl/generic_cache/VX_bank.v
View File

0
hw/rtl/VX_cache/VX_cache.v → hw/rtl/generic_cache/VX_cache.v
View File

0
hw/rtl/VX_cache/VX_cache_config.v → hw/rtl/generic_cache/VX_cache_config.v
View File

0
hw/rtl/VX_cache/VX_cache_core_req_bank_sel.v → hw/rtl/generic_cache/VX_cache_core_req_bank_sel.v
View File

0
hw/rtl/VX_cache/VX_cache_dfq_queue.v → hw/rtl/generic_cache/VX_cache_dfq_queue.v
View File

0
hw/rtl/VX_cache/VX_cache_dram_req_arb.v → hw/rtl/generic_cache/VX_cache_dram_req_arb.v
View File

0
hw/rtl/VX_cache/VX_cache_miss_resrv.v → hw/rtl/generic_cache/VX_cache_miss_resrv.v
View File

0
hw/rtl/VX_cache/VX_cache_req_queue.v → hw/rtl/generic_cache/VX_cache_req_queue.v
View File

0
hw/rtl/VX_cache/VX_cache_wb_sel_merge.v → hw/rtl/generic_cache/VX_cache_wb_sel_merge.v
View File

0
hw/rtl/VX_cache/VX_dcache_llv_resp_bank_sel.v → hw/rtl/generic_cache/VX_dcache_llv_resp_bank_sel.v
View File

0
hw/rtl/VX_cache/VX_fill_invalidator.v → hw/rtl/generic_cache/VX_fill_invalidator.v
View File

0
hw/rtl/VX_cache/VX_mrv_queue.v → hw/rtl/generic_cache/VX_mrv_queue.v
View File

0
hw/rtl/VX_cache/VX_prefetcher.v → hw/rtl/generic_cache/VX_prefetcher.v
View File

0
hw/rtl/VX_cache/VX_snp_fwd_arb.v → hw/rtl/generic_cache/VX_snp_fwd_arb.v
View File

0
hw/rtl/VX_cache/VX_tag_data_access.v → hw/rtl/generic_cache/VX_tag_data_access.v
View File

0
hw/rtl/VX_cache/VX_tag_data_structure.v → hw/rtl/generic_cache/VX_tag_data_structure.v
View File