89 lines
4.5 KiB
Tcl
89 lines
4.5 KiB
Tcl
package require cmdline
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set options { \
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{ "project.arg" "" "Project name" } \
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{ "family.arg" "" "Device family name" } \
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{ "device.arg" "" "Device name" } \
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{ "top.arg" "" "Top level module" } \
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{ "sdc.arg" "" "Timing Design Constraints file" } \
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{ "src.arg" "" "Verilog source file" } \
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}
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array set opts [::cmdline::getoptions quartus(args) $options]
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project_new $opts(project) -overwrite
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set_global_assignment -name FAMILY $opts(family)
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set_global_assignment -name DEVICE $opts(device)
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set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
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set_global_assignment -name SEARCH_PATH ../
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set_global_assignment -name VERILOG_FILE ../VX_define.v
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set_global_assignment -name VERILOG_FILE ../byte_enabled_simple_dual_port_ram.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_branch_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_csr_write_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_dcache_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_csr_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_exe_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_mem_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_reqeust_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_forward_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_frE_to_bckE_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_clone_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_jal_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_read_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_gpr_wspawn_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_request_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_icache_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_mem_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_inst_meta_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_jal_response_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_mem_req_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_mw_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_warp_ctl_inter.v
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set_global_assignment -name VERILOG_FILE ../interfaces/VX_wb_inter.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_d_e_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_e_m_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_f_d_reg.v
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set_global_assignment -name VERILOG_FILE ../pipe_regs/VX_m_w_reg.v
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set_global_assignment -name VERILOG_FILE ../VX_alu.v
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set_global_assignment -name VERILOG_FILE ../VX_back_end.v
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set_global_assignment -name VERILOG_FILE ../VX_context.v
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set_global_assignment -name VERILOG_FILE ../VX_context_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_csr_handler.v
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set_global_assignment -name VERILOG_FILE ../VX_decode.v
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set_global_assignment -name VERILOG_FILE ../VX_define.v
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set_global_assignment -name VERILOG_FILE ../VX_execute.v
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set_global_assignment -name VERILOG_FILE ../VX_fetch.v
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set_global_assignment -name VERILOG_FILE ../VX_forwarding.v
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set_global_assignment -name VERILOG_FILE ../VX_front_end.v
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set_global_assignment -name VERILOG_FILE ../VX_generic_register.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr_wrapper.v
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set_global_assignment -name VERILOG_FILE ../VX_gpr_syn.v
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set_global_assignment -name VERILOG_FILE ../VX_memory.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file_master_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_register_file_slave.v
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set_global_assignment -name VERILOG_FILE ../VX_warp.v
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set_global_assignment -name VERILOG_FILE ../VX_writeback.v
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set_global_assignment -name VERILOG_FILE ../Vortex.v
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set_global_assignment -name SDC_FILE vortex.sdc
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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project_close
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# set_global_assignment -name VERILOG_FILE $opts(src)
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